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davemgreendavemgreen
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[AArch64][GlobalISel] Update GISel check line and regenerate tests. NFC
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5 files changed

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‎llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir

Lines changed: 86 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,12 @@ body: |
1212
1313
; CHECK-LABEL: name: v16s8_gpr
1414
; CHECK: liveins: $q1, $w0
15-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
16-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
17-
; CHECK: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]]
18-
; CHECK: $q0 = COPY [[INSvi8gpr]]
19-
; CHECK: RET_ReallyLR implicit $q0
15+
; CHECK-NEXT: {{ $}}
16+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
17+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
18+
; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]]
19+
; CHECK-NEXT: $q0 = COPY [[INSvi8gpr]]
20+
; CHECK-NEXT: RET_ReallyLR implicit $q0
2021
%0:gpr(s32) = COPY $w0
2122
%trunc:gpr(s8) = G_TRUNC %0
2223
%1:fpr(<16 x s8>) = COPY $q1
@@ -38,14 +39,15 @@ body: |
3839
3940
; CHECK-LABEL: name: v8s8_gpr
4041
; CHECK: liveins: $d0, $w0
41-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
42-
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
43-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
44-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
45-
; CHECK: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[INSERT_SUBREG]], 1, [[COPY]]
46-
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub
47-
; CHECK: $d0 = COPY [[COPY2]]
48-
; CHECK: RET_ReallyLR implicit $d0
42+
; CHECK-NEXT: {{ $}}
43+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
44+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
45+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
46+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
47+
; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[INSERT_SUBREG]], 1, [[COPY]]
48+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub
49+
; CHECK-NEXT: $d0 = COPY [[COPY2]]
50+
; CHECK-NEXT: RET_ReallyLR implicit $d0
4951
%0:gpr(s32) = COPY $w0
5052
%trunc:gpr(s8) = G_TRUNC %0
5153
%1:fpr(<8 x s8>) = COPY $d0
@@ -67,11 +69,12 @@ body: |
6769
6870
; CHECK-LABEL: name: v8s16_gpr
6971
; CHECK: liveins: $q1, $w0
70-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
71-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
72-
; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
73-
; CHECK: $q0 = COPY [[INSvi16gpr]]
74-
; CHECK: RET_ReallyLR implicit $q0
72+
; CHECK-NEXT: {{ $}}
73+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
74+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
75+
; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
76+
; CHECK-NEXT: $q0 = COPY [[INSvi16gpr]]
77+
; CHECK-NEXT: RET_ReallyLR implicit $q0
7578
%0:gpr(s32) = COPY $w0
7679
%trunc:gpr(s16) = G_TRUNC %0
7780
%1:fpr(<8 x s16>) = COPY $q1
@@ -93,13 +96,14 @@ body: |
9396
9497
; CHECK-LABEL: name: v8s16_fpr
9598
; CHECK: liveins: $q1, $h0
96-
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
97-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
98-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
99-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
100-
; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
101-
; CHECK: $q0 = COPY [[INSvi16lane]]
102-
; CHECK: RET_ReallyLR implicit $q0
99+
; CHECK-NEXT: {{ $}}
100+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
101+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
102+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
103+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
104+
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
105+
; CHECK-NEXT: $q0 = COPY [[INSvi16lane]]
106+
; CHECK-NEXT: RET_ReallyLR implicit $q0
103107
%0:fpr(s16) = COPY $h0
104108
%1:fpr(<8 x s16>) = COPY $q1
105109
%3:gpr(s32) = G_CONSTANT i32 1
@@ -120,13 +124,14 @@ body: |
120124
121125
; CHECK-LABEL: name: v4s32_fpr
122126
; CHECK: liveins: $q1, $s0
123-
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
124-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
125-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
126-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
127-
; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
128-
; CHECK: $q0 = COPY [[INSvi32lane]]
129-
; CHECK: RET_ReallyLR implicit $q0
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
129+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
130+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
131+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
132+
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
133+
; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]
134+
; CHECK-NEXT: RET_ReallyLR implicit $q0
130135
%0:fpr(s32) = COPY $s0
131136
%1:fpr(<4 x s32>) = COPY $q1
132137
%3:gpr(s32) = G_CONSTANT i32 1
@@ -147,11 +152,12 @@ body: |
147152
148153
; CHECK-LABEL: name: v4s32_gpr
149154
; CHECK: liveins: $q0, $w0
150-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
151-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
152-
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
153-
; CHECK: $q0 = COPY [[INSvi32gpr]]
154-
; CHECK: RET_ReallyLR implicit $q0
155+
; CHECK-NEXT: {{ $}}
156+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
157+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
158+
; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
159+
; CHECK-NEXT: $q0 = COPY [[INSvi32gpr]]
160+
; CHECK-NEXT: RET_ReallyLR implicit $q0
155161
%0:gpr(s32) = COPY $w0
156162
%1:fpr(<4 x s32>) = COPY $q0
157163
%3:gpr(s32) = G_CONSTANT i32 1
@@ -172,14 +178,15 @@ body: |
172178
173179
; CHECK-LABEL: name: v4s16_gpr
174180
; CHECK: liveins: $d0, $w0
175-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
176-
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
177-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
178-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
179-
; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[INSERT_SUBREG]], 1, [[COPY]]
180-
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub
181-
; CHECK: $d0 = COPY [[COPY2]]
182-
; CHECK: RET_ReallyLR implicit $d0
181+
; CHECK-NEXT: {{ $}}
182+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
183+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
184+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
185+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
186+
; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[INSERT_SUBREG]], 1, [[COPY]]
187+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub
188+
; CHECK-NEXT: $d0 = COPY [[COPY2]]
189+
; CHECK-NEXT: RET_ReallyLR implicit $d0
183190
%0:gpr(s32) = COPY $w0
184191
%trunc:gpr(s16) = G_TRUNC %0
185192
%1:fpr(<4 x s16>) = COPY $d0
@@ -201,13 +208,14 @@ body: |
201208
202209
; CHECK-LABEL: name: v2s64_fpr
203210
; CHECK: liveins: $d0, $q1
204-
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
205-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
206-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
207-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
208-
; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
209-
; CHECK: $q0 = COPY [[INSvi64lane]]
210-
; CHECK: RET_ReallyLR implicit $q0
211+
; CHECK-NEXT: {{ $}}
212+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
213+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
214+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
215+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
216+
; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
217+
; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
218+
; CHECK-NEXT: RET_ReallyLR implicit $q0
211219
%0:fpr(s64) = COPY $d0
212220
%1:fpr(<2 x s64>) = COPY $q1
213221
%3:gpr(s32) = G_CONSTANT i32 1
@@ -228,11 +236,12 @@ body: |
228236
229237
; CHECK-LABEL: name: v2s64_gpr
230238
; CHECK: liveins: $q0, $x0
231-
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
232-
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
233-
; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
234-
; CHECK: $q0 = COPY [[INSvi64gpr]]
235-
; CHECK: RET_ReallyLR implicit $q0
239+
; CHECK-NEXT: {{ $}}
240+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
241+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
242+
; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
243+
; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]
244+
; CHECK-NEXT: RET_ReallyLR implicit $q0
236245
%0:gpr(s64) = COPY $x0
237246
%1:fpr(<2 x s64>) = COPY $q0
238247
%3:gpr(s32) = G_CONSTANT i32 0
@@ -253,16 +262,17 @@ body: |
253262
254263
; CHECK-LABEL: name: v2s32_fpr
255264
; CHECK: liveins: $d1, $s0
256-
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
257-
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
258-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
259-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
260-
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
261-
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
262-
; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
263-
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
264-
; CHECK: $d0 = COPY [[COPY2]]
265-
; CHECK: RET_ReallyLR implicit $d0
265+
; CHECK-NEXT: {{ $}}
266+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
267+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
268+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
269+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
270+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
271+
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
272+
; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
273+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
274+
; CHECK-NEXT: $d0 = COPY [[COPY2]]
275+
; CHECK-NEXT: RET_ReallyLR implicit $d0
266276
%0:fpr(s32) = COPY $s0
267277
%1:fpr(<2 x s32>) = COPY $d1
268278
%3:gpr(s32) = G_CONSTANT i32 1
@@ -283,14 +293,15 @@ body: |
283293
284294
; CHECK-LABEL: name: v2s32_gpr
285295
; CHECK: liveins: $d0, $w0
286-
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
287-
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
288-
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
289-
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
290-
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
291-
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
292-
; CHECK: $d0 = COPY [[COPY2]]
293-
; CHECK: RET_ReallyLR implicit $d0
296+
; CHECK-NEXT: {{ $}}
297+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
298+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
299+
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
300+
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
301+
; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
302+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
303+
; CHECK-NEXT: $d0 = COPY [[COPY2]]
304+
; CHECK-NEXT: RET_ReallyLR implicit $d0
294305
%0:gpr(s32) = COPY $w0
295306
%1:fpr(<2 x s32>) = COPY $d0
296307
%3:gpr(s32) = G_CONSTANT i32 1

‎llvm/test/CodeGen/AArch64/arm64-fminv.ll

Lines changed: 51 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,30 @@
1-
; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
2-
; RUN: llc -global-isel=1 -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
3+
; RUN: llc < %s -mtriple=arm64-linux-gnu -global-isel | FileCheck %s
34

45
define float @test_fminv_v2f32(<2 x float> %in) {
5-
; CHECK: test_fminv_v2f32:
6-
; CHECK: fminp s0, v0.2s
6+
; CHECK-LABEL: test_fminv_v2f32:
7+
; CHECK: // %bb.0:
8+
; CHECK-NEXT: fminp s0, v0.2s
9+
; CHECK-NEXT: ret
710
%min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)
811
ret float %min
912
}
1013

1114
define float @test_fminv_v4f32(<4 x float> %in) {
12-
; CHECK: test_fminv_v4f32:
13-
; CHECK: fminv s0, v0.4s
15+
; CHECK-LABEL: test_fminv_v4f32:
16+
; CHECK: // %bb.0:
17+
; CHECK-NEXT: fminv s0, v0.4s
18+
; CHECK-NEXT: ret
1419
%min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)
1520
ret float %min
1621
}
1722

1823
define double @test_fminv_v2f64(<2 x double> %in) {
19-
; CHECK: test_fminv_v2f64:
20-
; CHECK: fminp d0, v0.2d
24+
; CHECK-LABEL: test_fminv_v2f64:
25+
; CHECK: // %bb.0:
26+
; CHECK-NEXT: fminp d0, v0.2d
27+
; CHECK-NEXT: ret
2128
%min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)
2229
ret double %min
2330
}
@@ -27,22 +34,28 @@ declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
2734
declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
2835

2936
define float @test_fmaxv_v2f32(<2 x float> %in) {
30-
; CHECK: test_fmaxv_v2f32:
31-
; CHECK: fmaxp s0, v0.2s
37+
; CHECK-LABEL: test_fmaxv_v2f32:
38+
; CHECK: // %bb.0:
39+
; CHECK-NEXT: fmaxp s0, v0.2s
40+
; CHECK-NEXT: ret
3241
%max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)
3342
ret float %max
3443
}
3544

3645
define float @test_fmaxv_v4f32(<4 x float> %in) {
37-
; CHECK: test_fmaxv_v4f32:
38-
; CHECK: fmaxv s0, v0.4s
46+
; CHECK-LABEL: test_fmaxv_v4f32:
47+
; CHECK: // %bb.0:
48+
; CHECK-NEXT: fmaxv s0, v0.4s
49+
; CHECK-NEXT: ret
3950
%max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)
4051
ret float %max
4152
}
4253

4354
define double @test_fmaxv_v2f64(<2 x double> %in) {
44-
; CHECK: test_fmaxv_v2f64:
45-
; CHECK: fmaxp d0, v0.2d
55+
; CHECK-LABEL: test_fmaxv_v2f64:
56+
; CHECK: // %bb.0:
57+
; CHECK-NEXT: fmaxp d0, v0.2d
58+
; CHECK-NEXT: ret
4659
%max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in)
4760
ret double %max
4861
}
@@ -52,22 +65,28 @@ declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
5265
declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>)
5366

5467
define float @test_fminnmv_v2f32(<2 x float> %in) {
55-
; CHECK: test_fminnmv_v2f32:
56-
; CHECK: fminnmp s0, v0.2s
68+
; CHECK-LABEL: test_fminnmv_v2f32:
69+
; CHECK: // %bb.0:
70+
; CHECK-NEXT: fminnmp s0, v0.2s
71+
; CHECK-NEXT: ret
5772
%minnm = call float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float> %in)
5873
ret float %minnm
5974
}
6075

6176
define float @test_fminnmv_v4f32(<4 x float> %in) {
62-
; CHECK: test_fminnmv_v4f32:
63-
; CHECK: fminnmv s0, v0.4s
77+
; CHECK-LABEL: test_fminnmv_v4f32:
78+
; CHECK: // %bb.0:
79+
; CHECK-NEXT: fminnmv s0, v0.4s
80+
; CHECK-NEXT: ret
6481
%minnm = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %in)
6582
ret float %minnm
6683
}
6784

6885
define double @test_fminnmv_v2f64(<2 x double> %in) {
69-
; CHECK: test_fminnmv_v2f64:
70-
; CHECK: fminnmp d0, v0.2d
86+
; CHECK-LABEL: test_fminnmv_v2f64:
87+
; CHECK: // %bb.0:
88+
; CHECK-NEXT: fminnmp d0, v0.2d
89+
; CHECK-NEXT: ret
7190
%minnm = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in)
7291
ret double %minnm
7392
}
@@ -77,22 +96,28 @@ declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
7796
declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>)
7897

7998
define float @test_fmaxnmv_v2f32(<2 x float> %in) {
80-
; CHECK: test_fmaxnmv_v2f32:
81-
; CHECK: fmaxnmp s0, v0.2s
99+
; CHECK-LABEL: test_fmaxnmv_v2f32:
100+
; CHECK: // %bb.0:
101+
; CHECK-NEXT: fmaxnmp s0, v0.2s
102+
; CHECK-NEXT: ret
82103
%maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %in)
83104
ret float %maxnm
84105
}
85106

86107
define float @test_fmaxnmv_v4f32(<4 x float> %in) {
87-
; CHECK: test_fmaxnmv_v4f32:
88-
; CHECK: fmaxnmv s0, v0.4s
108+
; CHECK-LABEL: test_fmaxnmv_v4f32:
109+
; CHECK: // %bb.0:
110+
; CHECK-NEXT: fmaxnmv s0, v0.4s
111+
; CHECK-NEXT: ret
89112
%maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %in)
90113
ret float %maxnm
91114
}
92115

93116
define double @test_fmaxnmv_v2f64(<2 x double> %in) {
94-
; CHECK: test_fmaxnmv_v2f64:
95-
; CHECK: fmaxnmp d0, v0.2d
117+
; CHECK-LABEL: test_fmaxnmv_v2f64:
118+
; CHECK: // %bb.0:
119+
; CHECK-NEXT: fmaxnmp d0, v0.2d
120+
; CHECK-NEXT: ret
96121
%maxnm = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
97122
ret double %maxnm
98123
}

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