@@ -19087,7 +19087,7 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
19087
19087
State.getMachineFunction().getSubtarget<RISCVSubtarget>();
19088
19088
ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(STI.getTargetABI());
19089
19089
19090
- if (Register Reg = State.AllocateReg(ArgGPRs)) {
19090
+ if (MCRegister Reg = State.AllocateReg(ArgGPRs)) {
19091
19091
// At least one half can be passed via register.
19092
19092
State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
19093
19093
VA1.getLocVT(), CCValAssign::Full));
@@ -19108,7 +19108,7 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
19108
19108
return false;
19109
19109
}
19110
19110
19111
- if (Register Reg = State.AllocateReg(ArgGPRs)) {
19111
+ if (MCRegister Reg = State.AllocateReg(ArgGPRs)) {
19112
19112
// The second half can also be passed via register.
19113
19113
State.addLoc(
19114
19114
CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
@@ -19230,7 +19230,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
19230
19230
19231
19231
if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::bf16 ||
19232
19232
(ValVT == MVT::f32 && XLen == 64))) {
19233
- Register Reg = State.AllocateReg(ArgGPRs);
19233
+ MCRegister Reg = State.AllocateReg(ArgGPRs);
19234
19234
if (Reg) {
19235
19235
LocVT = XLenVT;
19236
19236
State.addLoc(
@@ -19283,7 +19283,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
19283
19283
// GPRs, split between a GPR and the stack, or passed completely on the
19284
19284
// stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
19285
19285
// cases.
19286
- Register Reg = State.AllocateReg(ArgGPRs);
19286
+ MCRegister Reg = State.AllocateReg(ArgGPRs);
19287
19287
if (!Reg) {
19288
19288
unsigned StackOffset = State.AllocateStack(8, Align(8));
19289
19289
State.addLoc(
@@ -19292,7 +19292,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
19292
19292
}
19293
19293
LocVT = MVT::i32;
19294
19294
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
19295
- Register HiReg = State.AllocateReg(ArgGPRs);
19295
+ MCRegister HiReg = State.AllocateReg(ArgGPRs);
19296
19296
if (HiReg) {
19297
19297
State.addLoc(
19298
19298
CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo));
@@ -19340,7 +19340,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
19340
19340
}
19341
19341
19342
19342
// Allocate to a register if possible, or else a stack slot.
19343
- Register Reg;
19343
+ MCRegister Reg;
19344
19344
unsigned StoreSizeBytes = XLen / 8;
19345
19345
Align StackAlign = Align(XLen / 8);
19346
19346
0 commit comments