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[AArch64][GlobalISel] Add support for widening vector store elements to s8.
Reviewers: topperc, arsenm, davemgreen Reviewed By: arsenm Pull Request: #121170
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3 files changed

+46
-2
lines changed

3 files changed

+46
-2
lines changed

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3022,8 +3022,19 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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return UnableToLegalize;
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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if (!Ty.isScalar())
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return UnableToLegalize;
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assert(!Ty.isPointerOrPointerVector() && "Can't widen type");
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if (!Ty.isScalar()) {
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// We need to widen the vector element type.
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Observer.changingInstr(MI);
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widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
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// We also need to adjust the MMO to turn this into a truncating store.
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MachineMemOperand &MMO = **MI.memoperands_begin();
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MachineFunction &MF = MIRBuilder.getMF();
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auto *NewMMO = MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), Ty);
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MI.setMemRefs(MF, {NewMMO});
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Observer.changedInstr(MI);
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return Legalized;
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}
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Observer.changingInstr(MI);
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llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -454,6 +454,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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{nxv2s64, p0, nxv2s64, 8},
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})
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.clampScalar(0, s8, s64)
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.minScalarOrElt(0, s8)
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.lowerIf([=](const LegalityQuery &Query) {
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return Query.Types[0].isScalar() &&
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Query.Types[0] != Query.MMODescrs[0].MemoryTy;
Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=2 %s -o - | FileCheck %s
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# This test currently is expected to fall back after reaching truncstore of <8 x s8> as <8 x s1>.
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---
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name: store_8xs1
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0, $q1, $x0
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; CHECK-LABEL: name: store_8xs1
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; CHECK: liveins: $q0, $q1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK-NEXT: %ptr:_(p0) = COPY $x0
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; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[COPY]](<4 x s32>), [[COPY1]](<4 x s32>)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s1>) = G_ICMP intpred(slt), [[CONCAT_VECTORS]](<8 x s32>), [[BUILD_VECTOR]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s8>) = G_ANYEXT [[ICMP]](<8 x s1>)
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; CHECK-NEXT: G_STORE [[ANYEXT]](<8 x s8>), %ptr(p0) :: (store (<8 x s1>))
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; CHECK-NEXT: RET_ReallyLR
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%1:_(<4 x s32>) = COPY $q0
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%2:_(<4 x s32>) = COPY $q1
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%ptr:_(p0) = COPY $x0
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%0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
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%4:_(s32) = G_CONSTANT i32 0
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%3:_(<8 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32)
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%5:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s32>), %3
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G_STORE %5(<8 x s1>), %ptr(p0) :: (store (<8 x s1>))
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RET_ReallyLR
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...

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