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tangaactangaac
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lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT
1 parent 64c2156 commit 7e36c8d

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5 files changed

+140
-4
lines changed

5 files changed

+140
-4
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -255,6 +255,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
255255
setOperationAction(ISD::SETCC, VT, Legal);
256256
setOperationAction(ISD::VSELECT, VT, Legal);
257257
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
258+
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
258259
}
259260
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) {
260261
setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal);
@@ -311,6 +312,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
311312
setOperationAction(ISD::SETCC, VT, Legal);
312313
setOperationAction(ISD::VSELECT, VT, Legal);
313314
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
315+
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
314316
}
315317
for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) {
316318
setOperationAction({ISD::ADD, ISD::SUB}, VT, Legal);
@@ -446,10 +448,26 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
446448
return lowerVECTOR_SHUFFLE(Op, DAG);
447449
case ISD::BITREVERSE:
448450
return lowerBITREVERSE(Op, DAG);
451+
case ISD::SCALAR_TO_VECTOR:
452+
return lowerSCALAR_TO_VECTOR(Op, DAG);
449453
}
450454
return SDValue();
451455
}
452456

457+
SDValue
458+
LoongArchTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
459+
SelectionDAG &DAG) const {
460+
SDLoc DL(Op);
461+
MVT OpVT = Op.getSimpleValueType();
462+
463+
SDValue Vector = DAG.getUNDEF(OpVT);
464+
SDValue Val = Op.getOperand(0);
465+
SDValue Idx = DAG.getConstant(0, DL, Subtarget.getGRLenVT());
466+
467+
Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, OpVT, Vector, Val, Idx);
468+
return Vector;
469+
}
470+
453471
SDValue LoongArchTargetLowering::lowerBITREVERSE(SDValue Op,
454472
SelectionDAG &DAG) const {
455473
EVT ResTy = Op->getValueType(0);

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,7 @@ class LoongArchTargetLowering : public TargetLowering {
336336
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
337337
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
338338
SDValue lowerBITREVERSE(SDValue Op, SelectionDAG &DAG) const;
339+
SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
339340

340341
bool isFPImmLegal(const APFloat &Imm, EVT VT,
341342
bool ForCodeSize) const override;

‎llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
; Test scalar_to_vector expansion.
5+
6+
define <32 x i8> @scalar_to_32xi8(i8 %val) {
7+
; CHECK-LABEL: scalar_to_32xi8:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%ret = insertelement <32 x i8> undef, i8 %val, i32 0
12+
ret <32 x i8> %ret
13+
}
14+
15+
define <16 x i16> @scalar_to_16xi16(i16 %val) {
16+
; CHECK-LABEL: scalar_to_16xi16:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
19+
; CHECK-NEXT: ret
20+
%ret = insertelement <16 x i16> undef, i16 %val, i32 0
21+
ret <16 x i16> %ret
22+
}
23+
24+
define <8 x i32> @scalar_to_8xi32(i32 %val) {
25+
; CHECK-LABEL: scalar_to_8xi32:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
28+
; CHECK-NEXT: ret
29+
%ret = insertelement <8 x i32> undef, i32 %val, i32 0
30+
ret <8 x i32> %ret
31+
}
32+
33+
define <4 x i64> @scalar_to_4xi64(i64 %val) {
34+
; CHECK-LABEL: scalar_to_4xi64:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
37+
; CHECK-NEXT: ret
38+
%ret = insertelement <4 x i64> undef, i64 %val, i32 0
39+
ret <4 x i64> %ret
40+
}
41+
42+
define <8 x float> @scalar_to_8xf32(float %val) {
43+
; CHECK-LABEL: scalar_to_8xf32:
44+
; CHECK: # %bb.0:
45+
; CHECK-NEXT: movfr2gr.s $a0, $fa0
46+
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
47+
; CHECK-NEXT: ret
48+
%ret = insertelement <8 x float> undef, float %val, i32 0
49+
ret <8 x float> %ret
50+
}
51+
52+
define <4 x double> @scalar_to_4xf64(double %val) {
53+
; CHECK-LABEL: scalar_to_4xf64:
54+
; CHECK: # %bb.0:
55+
; CHECK-NEXT: movfr2gr.d $a0, $fa0
56+
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
57+
; CHECK-NEXT: ret
58+
%ret = insertelement <4 x double> undef, double %val, i32 0
59+
ret <4 x double> %ret
60+
}

‎llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3+
4+
; Test scalar_to_vector expansion.
5+
6+
define <16 x i8> @scalar_to_16xi8(i8 %val) {
7+
; CHECK-LABEL: scalar_to_16xi8:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%ret = insertelement <16 x i8> undef, i8 %val, i32 0
12+
ret <16 x i8> %ret
13+
}
14+
15+
define <8 x i16> @scalar_to_8xi16(i16 %val) {
16+
; CHECK-LABEL: scalar_to_8xi16:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
19+
; CHECK-NEXT: ret
20+
%ret = insertelement <8 x i16> undef, i16 %val, i32 0
21+
ret <8 x i16> %ret
22+
}
23+
24+
define <4 x i32> @scalar_to_4xi32(i32 %val) {
25+
; CHECK-LABEL: scalar_to_4xi32:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
28+
; CHECK-NEXT: ret
29+
%ret = insertelement <4 x i32> undef, i32 %val, i32 0
30+
ret <4 x i32> %ret
31+
}
32+
33+
define <2 x i64> @scalar_to_2xi64(i64 %val) {
34+
; CHECK-LABEL: scalar_to_2xi64:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
37+
; CHECK-NEXT: ret
38+
%ret = insertelement <2 x i64> undef, i64 %val, i32 0
39+
ret <2 x i64> %ret
40+
}
41+
42+
define <4 x float> @scalar_to_4xf32(float %val) {
43+
; CHECK-LABEL: scalar_to_4xf32:
44+
; CHECK: # %bb.0:
45+
; CHECK-NEXT: movfr2gr.s $a0, $fa0
46+
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
47+
; CHECK-NEXT: ret
48+
%ret = insertelement <4 x float> undef, float %val, i32 0
49+
ret <4 x float> %ret
50+
}
51+
52+
define <2 x double> @scalar_to_2xf64(double %val) {
53+
; CHECK-LABEL: scalar_to_2xf64:
54+
; CHECK: # %bb.0:
55+
; CHECK-NEXT: movfr2gr.d $a0, $fa0
56+
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
57+
; CHECK-NEXT: ret
58+
%ret = insertelement <2 x double> undef, double %val, i32 0
59+
ret <2 x double> %ret
60+
}

‎llvm/test/CodeGen/LoongArch/vector-fp-imm.ll

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -126,17 +126,14 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
126126
;
127127
; LA64D-LABEL: test_f2:
128128
; LA64D: # %bb.0:
129-
; LA64D-NEXT: addi.d $sp, $sp, -16
130129
; LA64D-NEXT: ld.d $a0, $a0, 0
131-
; LA64D-NEXT: st.d $a0, $sp, 0
132-
; LA64D-NEXT: vld $vr0, $sp, 0
130+
; LA64D-NEXT: vinsgr2vr.d $vr0, $a0, 0
133131
; LA64D-NEXT: lu12i.w $a0, 260096
134132
; LA64D-NEXT: lu52i.d $a0, $a0, 1024
135133
; LA64D-NEXT: vreplgr2vr.d $vr1, $a0
136134
; LA64D-NEXT: vfadd.s $vr0, $vr0, $vr1
137135
; LA64D-NEXT: vpickve2gr.d $a0, $vr0, 0
138136
; LA64D-NEXT: st.d $a0, $a1, 0
139-
; LA64D-NEXT: addi.d $sp, $sp, 16
140137
; LA64D-NEXT: ret
141138
%p = load %f2, ptr %P
142139
%R = fadd %f2 %p, < float 1.000000e+00, float 2.000000e+00 >

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