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[RISCV][GISel] Group the vector load/store legalizer actions together.
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llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 31 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,22 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
285285
{s32, p0, s16, 16},
286286
{s32, p0, s32, 32},
287287
{p0, p0, sXLen, XLen}});
288-
if (ST.hasVInstructions())
288+
auto &ExtLoadActions =
289+
getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
290+
.legalForTypesWithMemDesc({{s32, p0, s8, 8}, {s32, p0, s16, 16}});
291+
if (XLen == 64) {
292+
LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s8, 8},
293+
{s64, p0, s16, 16},
294+
{s64, p0, s32, 32},
295+
{s64, p0, s64, 64}});
296+
ExtLoadActions.legalForTypesWithMemDesc(
297+
{{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
298+
} else if (ST.hasStdExtD()) {
299+
LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
300+
}
301+
302+
// Vector loads/stores.
303+
if (ST.hasVInstructions()) {
289304
LoadStoreActions.legalForTypesWithMemDesc({{nxv2s8, p0, nxv2s8, 8},
290305
{nxv4s8, p0, nxv4s8, 8},
291306
{nxv8s8, p0, nxv8s8, 8},
@@ -302,38 +317,26 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
302317
{nxv8s32, p0, nxv8s32, 32},
303318
{nxv16s32, p0, nxv16s32, 32}});
304319

305-
auto &ExtLoadActions =
306-
getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
307-
.legalForTypesWithMemDesc({{s32, p0, s8, 8}, {s32, p0, s16, 16}});
308-
if (XLen == 64) {
309-
LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s8, 8},
310-
{s64, p0, s16, 16},
311-
{s64, p0, s32, 32},
312-
{s64, p0, s64, 64}});
313-
ExtLoadActions.legalForTypesWithMemDesc(
314-
{{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
315-
} else if (ST.hasStdExtD()) {
316-
LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
317-
}
318-
if (ST.hasVInstructions() && ST.getELen() == 64)
319-
LoadStoreActions.legalForTypesWithMemDesc({{nxv1s8, p0, nxv1s8, 8},
320-
{nxv1s16, p0, nxv1s16, 16},
321-
{nxv1s32, p0, nxv1s32, 32}});
320+
if (ST.getELen() == 64)
321+
LoadStoreActions.legalForTypesWithMemDesc({{nxv1s8, p0, nxv1s8, 8},
322+
{nxv1s16, p0, nxv1s16, 16},
323+
{nxv1s32, p0, nxv1s32, 32}});
322324

323-
if (ST.hasVInstructionsI64())
324-
LoadStoreActions.legalForTypesWithMemDesc({{nxv1s64, p0, nxv1s64, 64},
325+
if (ST.hasVInstructionsI64())
326+
LoadStoreActions.legalForTypesWithMemDesc({{nxv1s64, p0, nxv1s64, 64},
327+
{nxv2s64, p0, nxv2s64, 64},
328+
{nxv4s64, p0, nxv4s64, 64},
329+
{nxv8s64, p0, nxv8s64, 64}});
325330

326-
{nxv2s64, p0, nxv2s64, 64},
327-
{nxv4s64, p0, nxv4s64, 64},
328-
{nxv8s64, p0, nxv8s64, 64}});
331+
// we will take the custom lowering logic if we have scalable vector types
332+
// with non-standard alignments
333+
LoadStoreActions.customIf(
334+
LegalityPredicates::any(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
335+
typeIsLegalPtrVec(0, PtrVecTys, ST)));
336+
}
329337

330338
LoadStoreActions.widenScalarToNextPow2(0, /* MinSize = */ 8)
331339
.lowerIfMemSizeNotByteSizePow2()
332-
// we will take the custom lowering logic if we have scalable vector types
333-
// with non-standard alignments
334-
.customIf(LegalityPredicate(
335-
LegalityPredicates::any(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
336-
typeIsLegalPtrVec(0, PtrVecTys, ST))))
337340
.clampScalar(0, s32, sXLen)
338341
.lower();
339342

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