[X86] Add missing REQUIRES to test case for #114360

RKSimon · RKSimon · commit 7ed36b9ec614 · 2024-11-29T10:35:05.000Z
diff --git a/llvm/test/CodeGen/X86/pr114360.ll b/llvm/test/CodeGen/X86/pr114360.ll
@@ -1,4 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=x86_64-- -debug-counter=dagcombine=0 | FileCheck %s
 
 ; BUG: shrinkAndImmediate folds away the AND after the ZEXT has already been folded away to SUBREG_TO_REG losing implicit zext.

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,5 @@`
`1`	`1`	`; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5`
	`2`	`+; REQUIRES: asserts`
`2`	`3`	`; RUN: llc < %s -mtriple=x86_64-- -debug-counter=dagcombine=0 \| FileCheck %s`
`3`	`4`
`4`	`5`	`; BUG: shrinkAndImmediate folds away the AND after the ZEXT has already been folded away to SUBREG_TO_REG losing implicit zext.`