Revert "[GlobalISel][AArch64] Combine unmerge(G_EXT v, undef) to unmerge(v)."

This reverts commit 6b37a65.
Accindentally pushed before squashing.

Author: dzhidzhoev

llvm/lib/Target/AArch64/AArch64Combine.td

@@ -206,14 +206,6 @@ def vector_sext_inreg_to_shift : GICombineRule<
   (apply [{ applyVectorSextInReg(*${d}, MRI, B, Observer); }])
 >;
 
-def unmerge_ext_to_unmerge_matchdata : GIDefMatchData<"Register">;
-def unmerge_ext_to_unmerge : GICombineRule<
-  (defs root:$d, unmerge_ext_to_unmerge_matchdata:$matchinfo),
-  (match (wip_match_opcode G_UNMERGE_VALUES):$d,
-          [{ return matchUnmergeExtToUnmerge(*${d}, MRI, ${matchinfo}); }]),
-  (apply [{ applyUnmergeExtToUnmerge(*${d}, MRI, B, Observer, ${matchinfo}); }])
->;
-
 // Post-legalization combines which should happen at all optimization levels.
 // (E.g. ones that facilitate matching for the selector) For example, matching
 // pseudos.
@@ -222,8 +214,7 @@ def AArch64PostLegalizerLowering
                        [shuffle_vector_lowering, vashr_vlshr_imm,
                         icmp_lowering, build_vector_lowering,
                         lower_vector_fcmp, form_truncstore,
-                        vector_sext_inreg_to_shift,
-                        unmerge_ext_to_unmerge]> {
+                        vector_sext_inreg_to_shift]> {
 }
 
 // Post-legalization combines which are primarily optimizations.

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -1066,50 +1066,6 @@ void applyVectorSextInReg(MachineInstr &MI, MachineRegisterInfo &MRI,
   Helper.lower(MI, 0, /* Unused hint type */ LLT());
 }
 
-/// Combine <N x t>, unused = unmerge(G_EXT <2*N x t> v, undef, N)
-///           => unused, <N x t> = unmerge v
-bool matchUnmergeExtToUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
-                              Register &MatchInfo) {
-  auto &Unmerge = cast<GUnmerge>(MI);
-  if (Unmerge.getNumDefs() != 2)
-    return false;
-  if (!MRI.use_nodbg_empty(Unmerge.getReg(1)))
-    return false;
-
-  LLT DstTy = MRI.getType(Unmerge.getReg(0));
-  if (!DstTy.isVector())
-    return false;
-
-  MachineInstr *Ext = getOpcodeDef(AArch64::G_EXT, Unmerge.getSourceReg(), MRI);
-  if (!Ext)
-    return false;
-
-  Register ExtSrc1 = Ext->getOperand(1).getReg();
-  Register ExtSrc2 = Ext->getOperand(2).getReg();
-  auto LowestVal =
-      getIConstantVRegValWithLookThrough(Ext->getOperand(3).getReg(), MRI);
-  if (!LowestVal || LowestVal->Value.getZExtValue() != DstTy.getSizeInBytes())
-    return false;
-
-  if (!getOpcodeDef<GImplicitDef>(ExtSrc2, MRI))
-    return false;
-
-  MatchInfo = ExtSrc1;
-  return true;
-}
-
-void applyUnmergeExtToUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
-                              MachineIRBuilder &B,
-                              GISelChangeObserver &Observer, Register &SrcReg) {
-  Observer.changingInstr(MI);
-  // Swap dst registers.
-  Register Dst1 = MI.getOperand(0).getReg();
-  MI.getOperand(0).setReg(MI.getOperand(1).getReg());
-  MI.getOperand(1).setReg(Dst1);
-  MI.getOperand(2).setReg(SrcReg);
-  Observer.changedInstr(MI);
-}
-
 class AArch64PostLegalizerLoweringImpl : public Combiner {
 protected:
   // TODO: Make CombinerHelper methods const.

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir

@@ -137,7 +137,7 @@ define i32 @addp_v4i32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-GI-LABEL: addp_v4i32:
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    add v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT:    mov d1, v0.d[1]
+; CHECK-GI-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-GI-NEXT:    addp v0.2s, v0.2s, v1.2s
 ; CHECK-GI-NEXT:    rev64 v1.2s, v0.2s
 ; CHECK-GI-NEXT:    add v0.2s, v0.2s, v1.2s
@@ -164,7 +164,7 @@ define <4 x i16> @addp_v8i16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-GI-LABEL: addp_v8i16:
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    add v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT:    mov d1, v0.d[1]
+; CHECK-GI-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-GI-NEXT:    addp v0.4h, v0.4h, v1.4h
 ; CHECK-GI-NEXT:    ret
   %1 = add <8 x i16> %a, %b
@@ -185,7 +185,7 @@ define <8 x i8> @addp_v16i8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-GI-LABEL: addp_v16i8:
 ; CHECK-GI:       // %bb.0:
 ; CHECK-GI-NEXT:    add v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT:    mov d1, v0.d[1]
+; CHECK-GI-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
 ; CHECK-GI-NEXT:    addp v0.8b, v0.8b, v1.8b
 ; CHECK-GI-NEXT:    ret
   %1 = add <16 x i8> %a, %b