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michaelmaitlandmshockwave
michaelmaitland
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mshockwave
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[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)
The SiFiveP400 scheduler model did not support vector or vector crypto. With the addition of the sifive-p470 processor, this model needs to support these extensions. The processors who use this model but do not have vector or vector crypto will never produce these instructions, so there is no impact to these processors. Co-authored-by: Min Hsu <[email protected]>
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15 files changed

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15 files changed

+13631
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‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Lines changed: 867 additions & 2 deletions
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‎llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -42,15 +42,20 @@ fld ft0, 0(a0)
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# CHECK-NEXT: [5] - SiFiveP400IEXQ2
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# CHECK-NEXT: [6] - SiFiveP400Load
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# CHECK-NEXT: [7] - SiFiveP400Store
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# CHECK-NEXT: [8] - SiFiveP400VDiv
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# CHECK-NEXT: [9] - SiFiveP400VEXQ0
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# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
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# CHECK-NEXT: [11] - SiFiveP400VLD
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# CHECK-NEXT: [12] - SiFiveP400VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - - - - - 5.00 -
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
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# CHECK-NEXT: - - - - - - 5.00 - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - - - - - 1.00 - lw t0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - ld t0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - flh ft0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - flw ft0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - fld ft0, 0(a0)
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
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# CHECK-NEXT: - - - - - - 1.00 - - - - - - lw t0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - - - - - - ld t0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - - - - - - flw ft0, 0(a0)
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# CHECK-NEXT: - - - - - - 1.00 - - - - - - fld ft0, 0(a0)

‎llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s

Lines changed: 108 additions & 0 deletions
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@@ -0,0 +1,108 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
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vsetvli zero, zero, e32, m2, tu, mu
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vslidedown.vx v5, v7, x6
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vsetvli zero, zero, e32, m4, tu, mu
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vslidedown.vx v5, v7, x6
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vsetvli zero, zero, e32, m8, tu, mu
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vslidedown.vx v5, v7, x6
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vsetvli zero, zero, e32, m2, tu, mu
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vslideup.vx v5, v7, x6
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vsetvli zero, zero, e32, m4, tu, mu
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vslideup.vx v5, v7, x6
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vsetvli zero, zero, e32, m8, tu, mu
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vslideup.vx v5, v7, x6
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vsetvli zero, zero, e32, m2, tu, mu
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vslideup.vx v5, v7, x6, v0.t
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vsetvli zero, zero, e32, m4, tu, mu
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vslideup.vx v5, v7, x6, v0.t
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vsetvli zero, zero, e32, m8, tu, mu
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vslideup.vx v5, v7, x6, v0.t
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 18
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# CHECK-NEXT: Total Cycles: 125
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# CHECK-NEXT: Total uOps: 18
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# CHECK: Dispatch Width: 3
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# CHECK-NEXT: uOps Per Cycle: 0.14
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# CHECK-NEXT: IPC: 0.14
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# CHECK-NEXT: Block RThroughput: 121.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
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# CHECK-NEXT: 1 11 11.00 vslidedown.vx v5, v7, t1
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
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# CHECK-NEXT: 1 14 14.00 vslidedown.vx v5, v7, t1
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
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# CHECK-NEXT: 1 20 20.00 vslidedown.vx v5, v7, t1
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
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# CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
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# CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
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# CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
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# CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1, v0.t
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
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# CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1, v0.t
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
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# CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1, v0.t
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP400Div
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# CHECK-NEXT: [1] - SiFiveP400FEXQ0
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# CHECK-NEXT: [2] - SiFiveP400FloatDiv
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# CHECK-NEXT: [3] - SiFiveP400IEXQ0
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# CHECK-NEXT: [4] - SiFiveP400IEXQ1
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# CHECK-NEXT: [5] - SiFiveP400IEXQ2
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# CHECK-NEXT: [6] - SiFiveP400Load
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# CHECK-NEXT: [7] - SiFiveP400Store
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# CHECK-NEXT: [8] - SiFiveP400VDiv
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# CHECK-NEXT: [9] - SiFiveP400VEXQ0
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# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
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# CHECK-NEXT: [11] - SiFiveP400VLD
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# CHECK-NEXT: [12] - SiFiveP400VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
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# CHECK-NEXT: - - - - 9.00 - - - - 121.00 - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - 11.00 - - - vslidedown.vx v5, v7, t1
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - 14.00 - - - vslidedown.vx v5, v7, t1
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - 20.00 - - - vslidedown.vx v5, v7, t1
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
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# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1, v0.t
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
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# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1, v0.t
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
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# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1, v0.t
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