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[AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg (#140946)
select vgpr16 for asm inline 16bit vreg in true16 mode
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3 files changed

+172
-1
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3 files changed

+172
-1
lines changed

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16062,7 +16062,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
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case 'v':
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switch (BitWidth) {
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case 16:
16065-
RC = &AMDGPU::VGPR_32RegClass;
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RC = Subtarget->useRealTrue16Insts() ? &AMDGPU::VGPR_16RegClass
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: &AMDGPU::VGPR_32RegClass;
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break;
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default:
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RC = TRI->getVGPRClassForBitWidth(BitWidth);

‎llvm/test/CodeGen/AMDGPU/inlineasm-16-fake16.ll

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
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define amdgpu_kernel void @s_input_output_i16() #0 {
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; GFX11-LABEL: s_input_output_i16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: s_mov_b32 s0, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use s0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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%v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
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tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
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ret void
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}
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define amdgpu_kernel void @s_input_output_f16() #0 {
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; GFX11-LABEL: s_input_output_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: s_mov_b32 s0, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use s0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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%v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0
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tail call void asm sideeffect "; use $0", "s"(half %v)
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ret void
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}
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define amdgpu_kernel void @v_input_output_f16() #0 {
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; GFX11-LABEL: v_input_output_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: v_mov_b32 v0, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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%v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
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tail call void asm sideeffect "; use $0", "v"(half %v)
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ret void
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}
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define amdgpu_kernel void @v_input_output_i16() #0 {
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; GFX11-LABEL: v_input_output_i16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: v_mov_b32 v0, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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%v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
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tail call void asm sideeffect "; use $0", "v"(i16 %v)
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ret void
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}
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define amdgpu_kernel void @i16_imm_input_phys_vgpr() {
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; GFX11-LABEL: i16_imm_input_phys_vgpr:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: v_mov_b32_e32 v0, 0xffff
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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entry:
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call void asm sideeffect "; use $0 ", "{v0}"(i16 65535)
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ret void
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}
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attributes #0 = { nounwind }

‎llvm/test/CodeGen/AMDGPU/inlineasm-16-true16.ll

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
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define amdgpu_kernel void @s_input_output_i16() #0 {
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; GFX11-LABEL: s_input_output_i16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: s_mov_b32 s0, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use s0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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%v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
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tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
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ret void
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}
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define amdgpu_kernel void @s_input_output_f16() #0 {
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; GFX11-LABEL: s_input_output_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: s_mov_b32 s0, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use s0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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%v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0
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tail call void asm sideeffect "; use $0", "s"(half %v)
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ret void
33+
}
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define amdgpu_kernel void @v_input_output_f16() #0 {
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; GFX11-LABEL: v_input_output_f16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: v_mov_b16 v0.l, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0.l
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
45+
%v = tail call half asm sideeffect "v_mov_b16 $0, -1", "=v"() #0
46+
tail call void asm sideeffect "; use $0", "v"(half %v)
47+
ret void
48+
}
49+
50+
define amdgpu_kernel void @v_input_output_i16() #0 {
51+
; GFX11-LABEL: v_input_output_i16:
52+
; GFX11: ; %bb.0:
53+
; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: v_mov_b16 v0.l, -1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0.l
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
60+
%v = tail call i16 asm sideeffect "v_mov_b16 $0, -1", "=v"() #0
61+
tail call void asm sideeffect "; use $0", "v"(i16 %v)
62+
ret void
63+
}
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65+
define amdgpu_kernel void @i16_imm_input_phys_vgpr_lo() {
66+
; GFX11-LABEL: i16_imm_input_phys_vgpr_lo:
67+
; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: v_mov_b16_e32 v0.l, -1
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0.l
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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entry:
74+
call void asm sideeffect "; use $0 ", "{v0.l}"(i16 65535)
75+
ret void
76+
}
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define amdgpu_kernel void @i16_imm_input_phys_vgpr_hi() {
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; GFX11-LABEL: i16_imm_input_phys_vgpr_hi:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: v_mov_b16_e32 v0.h, -1
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use v0.h
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_endpgm
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entry:
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call void asm sideeffect "; use $0 ", "{v0.h}"(i16 65535)
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ret void
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}
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attributes #0 = { nounwind }

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