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jhuber6jhuber6
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x86 test
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‎clang/test/CodeGen/scoped-fence-ops.c

Lines changed: 147 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -1,53 +1,33 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
22
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \
33
// RUN: -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s
4-
//: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \
5-
//: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s
4+
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \
5+
// RUN: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s
6+
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-linux-gnu -ffreestanding \
7+
// RUN: -fvisibility=hidden | FileCheck --check-prefix=X86_64 %s
68

9+
// AMDGCN-LABEL: define hidden void @fe1a(
10+
// AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {
11+
// AMDGCN-NEXT: [[ENTRY:.*:]]
12+
// AMDGCN-NEXT: fence syncscope("workgroup-one-as") release
13+
// AMDGCN-NEXT: ret void
714
//
815
// SPIRV-LABEL: define hidden spir_func void @fe1a(
916
// SPIRV-SAME: ) #[[ATTR0:[0-9]+]] {
1017
// SPIRV-NEXT: [[ENTRY:.*:]]
1118
// SPIRV-NEXT: fence syncscope("workgroup") release
1219
// SPIRV-NEXT: ret void
13-
// AMDGCN-LABEL: define hidden void @fe1a(
14-
// AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {
15-
// AMDGCN-NEXT: [[ENTRY:.*:]]
16-
// AMDGCN-NEXT: fence syncscope("workgroup-one-as") release
17-
// AMDGCN-NEXT: ret void
20+
//
21+
// X86_64-LABEL: define hidden void @fe1a(
22+
// X86_64-SAME: ) #[[ATTR0:[0-9]+]] {
23+
// X86_64-NEXT: [[ENTRY:.*:]]
24+
// X86_64-NEXT: fence release
25+
// X86_64-NEXT: ret void
1826
//
1927
void fe1a() {
2028
__scoped_atomic_thread_fence(__ATOMIC_RELEASE, __MEMORY_SCOPE_WRKGRP);
2129
}
2230

23-
//
24-
// SPIRV-LABEL: define hidden spir_func void @fe1b(
25-
// SPIRV-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
26-
// SPIRV-NEXT: [[ENTRY:.*:]]
27-
// SPIRV-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4
28-
// SPIRV-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 4
29-
// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 4
30-
// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
31-
// SPIRV-NEXT: i32 1, label %[[ACQUIRE:.*]]
32-
// SPIRV-NEXT: i32 2, label %[[ACQUIRE]]
33-
// SPIRV-NEXT: i32 3, label %[[RELEASE:.*]]
34-
// SPIRV-NEXT: i32 4, label %[[ACQREL:.*]]
35-
// SPIRV-NEXT: i32 5, label %[[SEQCST:.*]]
36-
// SPIRV-NEXT: ]
37-
// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:
38-
// SPIRV-NEXT: ret void
39-
// SPIRV: [[ACQUIRE]]:
40-
// SPIRV-NEXT: fence syncscope("workgroup") acquire
41-
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
42-
// SPIRV: [[RELEASE]]:
43-
// SPIRV-NEXT: fence syncscope("workgroup") release
44-
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
45-
// SPIRV: [[ACQREL]]:
46-
// SPIRV-NEXT: fence syncscope("workgroup") acq_rel
47-
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
48-
// SPIRV: [[SEQCST]]:
49-
// SPIRV-NEXT: fence syncscope("workgroup") seq_cst
50-
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
5131
// AMDGCN-LABEL: define hidden void @fe1b(
5232
// AMDGCN-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
5333
// AMDGCN-NEXT: [[ENTRY:.*:]]
@@ -77,41 +57,66 @@ void fe1a() {
7757
// AMDGCN-NEXT: fence syncscope("workgroup") seq_cst
7858
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
7959
//
80-
void fe1b(int ord) {
81-
__scoped_atomic_thread_fence(ord, __MEMORY_SCOPE_WRKGRP);
82-
}
83-
84-
//
85-
// SPIRV-LABEL: define hidden spir_func void @fe1c(
86-
// SPIRV-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
60+
// SPIRV-LABEL: define hidden spir_func void @fe1b(
61+
// SPIRV-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
8762
// SPIRV-NEXT: [[ENTRY:.*:]]
88-
// SPIRV-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4
89-
// SPIRV-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4
90-
// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4
63+
// SPIRV-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4
64+
// SPIRV-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 4
65+
// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 4
9166
// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
92-
// SPIRV-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
93-
// SPIRV-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
94-
// SPIRV-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
95-
// SPIRV-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
96-
// SPIRV-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
67+
// SPIRV-NEXT: i32 1, label %[[ACQUIRE:.*]]
68+
// SPIRV-NEXT: i32 2, label %[[ACQUIRE]]
69+
// SPIRV-NEXT: i32 3, label %[[RELEASE:.*]]
70+
// SPIRV-NEXT: i32 4, label %[[ACQREL:.*]]
71+
// SPIRV-NEXT: i32 5, label %[[SEQCST:.*]]
9772
// SPIRV-NEXT: ]
9873
// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:
9974
// SPIRV-NEXT: ret void
100-
// SPIRV: [[DEVICE_SCOPE]]:
101-
// SPIRV-NEXT: fence syncscope("device") release
102-
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
103-
// SPIRV: [[SYSTEM_SCOPE]]:
104-
// SPIRV-NEXT: fence release
75+
// SPIRV: [[ACQUIRE]]:
76+
// SPIRV-NEXT: fence syncscope("workgroup") acquire
10577
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
106-
// SPIRV: [[WORKGROUP_SCOPE]]:
78+
// SPIRV: [[RELEASE]]:
10779
// SPIRV-NEXT: fence syncscope("workgroup") release
10880
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
109-
// SPIRV: [[WAVEFRONT_SCOPE]]:
110-
// SPIRV-NEXT: fence syncscope("subgroup") release
81+
// SPIRV: [[ACQREL]]:
82+
// SPIRV-NEXT: fence syncscope("workgroup") acq_rel
11183
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
112-
// SPIRV: [[SINGLE_SCOPE]]:
113-
// SPIRV-NEXT: fence syncscope("singlethread") release
84+
// SPIRV: [[SEQCST]]:
85+
// SPIRV-NEXT: fence syncscope("workgroup") seq_cst
11486
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
87+
//
88+
// X86_64-LABEL: define hidden void @fe1b(
89+
// X86_64-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
90+
// X86_64-NEXT: [[ENTRY:.*:]]
91+
// X86_64-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4
92+
// X86_64-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 4
93+
// X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 4
94+
// X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
95+
// X86_64-NEXT: i32 1, label %[[ACQUIRE:.*]]
96+
// X86_64-NEXT: i32 2, label %[[ACQUIRE]]
97+
// X86_64-NEXT: i32 3, label %[[RELEASE:.*]]
98+
// X86_64-NEXT: i32 4, label %[[ACQREL:.*]]
99+
// X86_64-NEXT: i32 5, label %[[SEQCST:.*]]
100+
// X86_64-NEXT: ]
101+
// X86_64: [[ATOMIC_SCOPE_CONTINUE]]:
102+
// X86_64-NEXT: ret void
103+
// X86_64: [[ACQUIRE]]:
104+
// X86_64-NEXT: fence acquire
105+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
106+
// X86_64: [[RELEASE]]:
107+
// X86_64-NEXT: fence release
108+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
109+
// X86_64: [[ACQREL]]:
110+
// X86_64-NEXT: fence acq_rel
111+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
112+
// X86_64: [[SEQCST]]:
113+
// X86_64-NEXT: fence seq_cst
114+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
115+
//
116+
void fe1b(int ord) {
117+
__scoped_atomic_thread_fence(ord, __MEMORY_SCOPE_WRKGRP);
118+
}
119+
115120
// AMDGCN-LABEL: define hidden void @fe1c(
116121
// AMDGCN-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
117122
// AMDGCN-NEXT: [[ENTRY:.*:]]
@@ -144,35 +149,108 @@ void fe1b(int ord) {
144149
// AMDGCN-NEXT: fence syncscope("singlethread-one-as") release
145150
// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
146151
//
152+
// SPIRV-LABEL: define hidden spir_func void @fe1c(
153+
// SPIRV-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
154+
// SPIRV-NEXT: [[ENTRY:.*:]]
155+
// SPIRV-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4
156+
// SPIRV-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4
157+
// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4
158+
// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
159+
// SPIRV-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
160+
// SPIRV-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
161+
// SPIRV-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
162+
// SPIRV-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
163+
// SPIRV-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
164+
// SPIRV-NEXT: ]
165+
// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:
166+
// SPIRV-NEXT: ret void
167+
// SPIRV: [[DEVICE_SCOPE]]:
168+
// SPIRV-NEXT: fence syncscope("device") release
169+
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
170+
// SPIRV: [[SYSTEM_SCOPE]]:
171+
// SPIRV-NEXT: fence release
172+
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
173+
// SPIRV: [[WORKGROUP_SCOPE]]:
174+
// SPIRV-NEXT: fence syncscope("workgroup") release
175+
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
176+
// SPIRV: [[WAVEFRONT_SCOPE]]:
177+
// SPIRV-NEXT: fence syncscope("subgroup") release
178+
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
179+
// SPIRV: [[SINGLE_SCOPE]]:
180+
// SPIRV-NEXT: fence syncscope("singlethread") release
181+
// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
182+
//
183+
// X86_64-LABEL: define hidden void @fe1c(
184+
// X86_64-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
185+
// X86_64-NEXT: [[ENTRY:.*:]]
186+
// X86_64-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4
187+
// X86_64-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4
188+
// X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4
189+
// X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
190+
// X86_64-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
191+
// X86_64-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
192+
// X86_64-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
193+
// X86_64-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
194+
// X86_64-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
195+
// X86_64-NEXT: ]
196+
// X86_64: [[ATOMIC_SCOPE_CONTINUE]]:
197+
// X86_64-NEXT: ret void
198+
// X86_64: [[DEVICE_SCOPE]]:
199+
// X86_64-NEXT: fence release
200+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
201+
// X86_64: [[SYSTEM_SCOPE]]:
202+
// X86_64-NEXT: fence release
203+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
204+
// X86_64: [[WORKGROUP_SCOPE]]:
205+
// X86_64-NEXT: fence release
206+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
207+
// X86_64: [[WAVEFRONT_SCOPE]]:
208+
// X86_64-NEXT: fence release
209+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
210+
// X86_64: [[SINGLE_SCOPE]]:
211+
// X86_64-NEXT: fence release
212+
// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
213+
//
147214
void fe1c(int scope) {
148215
__scoped_atomic_thread_fence(__ATOMIC_RELEASE, scope);
149216
}
150217

218+
// AMDGCN-LABEL: define hidden void @fe2a(
219+
// AMDGCN-SAME: ) #[[ATTR0]] {
220+
// AMDGCN-NEXT: [[ENTRY:.*:]]
221+
// AMDGCN-NEXT: ret void
151222
//
152223
// SPIRV-LABEL: define hidden spir_func void @fe2a(
153224
// SPIRV-SAME: ) #[[ATTR0]] {
154225
// SPIRV-NEXT: [[ENTRY:.*:]]
155226
// SPIRV-NEXT: ret void
156-
// AMDGCN-LABEL: define hidden void @fe2a(
157-
// AMDGCN-SAME: ) #[[ATTR0]] {
158-
// AMDGCN-NEXT: [[ENTRY:.*:]]
159-
// AMDGCN-NEXT: ret void
227+
//
228+
// X86_64-LABEL: define hidden void @fe2a(
229+
// X86_64-SAME: ) #[[ATTR0]] {
230+
// X86_64-NEXT: [[ENTRY:.*:]]
231+
// X86_64-NEXT: ret void
160232
//
161233
void fe2a() {
162234
__scoped_atomic_thread_fence(999, __MEMORY_SCOPE_SYSTEM);
163235
}
164236

237+
// AMDGCN-LABEL: define hidden void @fe2b(
238+
// AMDGCN-SAME: ) #[[ATTR0]] {
239+
// AMDGCN-NEXT: [[ENTRY:.*:]]
240+
// AMDGCN-NEXT: fence syncscope("one-as") release
241+
// AMDGCN-NEXT: ret void
165242
//
166243
// SPIRV-LABEL: define hidden spir_func void @fe2b(
167244
// SPIRV-SAME: ) #[[ATTR0]] {
168245
// SPIRV-NEXT: [[ENTRY:.*:]]
169246
// SPIRV-NEXT: fence release
170247
// SPIRV-NEXT: ret void
171-
// AMDGCN-LABEL: define hidden void @fe2b(
172-
// AMDGCN-SAME: ) #[[ATTR0]] {
173-
// AMDGCN-NEXT: [[ENTRY:.*:]]
174-
// AMDGCN-NEXT: fence syncscope("one-as") release
175-
// AMDGCN-NEXT: ret void
248+
//
249+
// X86_64-LABEL: define hidden void @fe2b(
250+
// X86_64-SAME: ) #[[ATTR0]] {
251+
// X86_64-NEXT: [[ENTRY:.*:]]
252+
// X86_64-NEXT: fence release
253+
// X86_64-NEXT: ret void
176254
//
177255
void fe2b() {
178256
__scoped_atomic_thread_fence(__ATOMIC_RELEASE, 999);

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