Fix test

Author: optimisan

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -2192,14 +2192,14 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
   addPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}));
   addPass(SILowerWWMCopiesPass());
   addPass(VirtRegRewriterPass(false));
-  // TODO: addPass(AMDGPUReserveWWMRegsPass());
+  addPass(AMDGPUReserveWWMRegsPass());
 
   // For allocating per-thread VGPRs.
   // addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
   addPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}));
 
 
-  // TODO: addPreRewrite();
+  addPreRewrite(addPass);
   addPass(VirtRegRewriterPass(true));
 
   // TODO: addPass(AMDGPUMarkLastScratchLoadPass());

llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir

@@ -1,6 +1,6 @@
 # RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
 
-# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virt-reg-rewriter,2 -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>,stack-slot-coloring,si-lower-sgpr-spills,si-pre-allocate-wwm-regs,greedy<wwm>,si-lower-wwm-copies,virt-reg-rewriter<no-clear-vregs>,amdgpu-reserve-wwm-regs,greedy<vgpr>,amdgpu-nsa-reassign,virt-reg-rewriter' -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
 # Using the unaligned vector tuples are OK as long as they aren't used
 # in a real instruction.