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[RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (#78021)
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6 files changed

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‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1064,12 +1064,12 @@
10641064
// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}}
10651065

10661066
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1067-
// RUN: -march=rv32izfbfmin0p8 -x c -E -dM %s \
1067+
// RUN: -march=rv32izfbfmin1p0 -x c -E -dM %s \
10681068
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
10691069
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1070-
// RUN: -march=rv64izfbfmin0p8 -x c -E -dM %s \
1070+
// RUN: -march=rv64izfbfmin1p0 -x c -E -dM %s \
10711071
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
1072-
// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}}
1072+
// CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 1000000{{$}}
10731073

10741074
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
10751075
// RUN: -march=rv32i_zicfilp0p4 -x c -E -dM %s \
@@ -1128,20 +1128,20 @@
11281128
// CHECK-ZVBC-EXT: __riscv_zvbc 1000000{{$}}
11291129

11301130
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1131-
// RUN: -march=rv32ifzvfbfmin0p8 -x c -E -dM %s \
1131+
// RUN: -march=rv32ifzvfbfmin1p0 -x c -E -dM %s \
11321132
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
11331133
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1134-
// RUN: -march=rv64ifzvfbfmin0p8 -x c -E -dM %s \
1134+
// RUN: -march=rv64ifzvfbfmin1p0 -x c -E -dM %s \
11351135
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s
1136-
// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 8000{{$}}
1136+
// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 1000000{{$}}
11371137

11381138
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1139-
// RUN: -march=rv32ifzvfbfwma0p8 -x c -E -dM %s \
1139+
// RUN: -march=rv32ifzvfbfwma1p0 -x c -E -dM %s \
11401140
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
11411141
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1142-
// RUN: -march=rv64ifzvfbfwma0p8 -x c -E -dM %s \
1142+
// RUN: -march=rv64ifzvfbfwma1p0 -x c -E -dM %s \
11431143
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
1144-
// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 8000{{$}}
1144+
// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 1000000{{$}}
11451145

11461146
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
11471147
// RUN: -march=rv32i_zve32x_zvkg1p0 -x c -E -dM %s \

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,7 @@ The primary goal of experimental support is to assist in the process of ratifica
216216
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
217217

218218
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
219-
LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.
219+
LLVM implements assembler support for the `1.0.0-rc2 specification <https://github.com/riscv/riscv-bfloat16/releases/tag/v59042fc71c31a9bcb2f1957621c960ed36fac401>`_.
220220

221221
``experimental-zicfilp``, ``experimental-zicfiss``
222222
LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__.

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
187187

188188
{"zcmop", {0, 2}},
189189

190-
{"zfbfmin", {0, 8}},
190+
{"zfbfmin", {1, 0}},
191191

192192
{"zicfilp", {0, 4}},
193193
{"zicfiss", {0, 4}},
@@ -198,8 +198,8 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
198198

199199
{"ztso", {0, 1}},
200200

201-
{"zvfbfmin", {0, 8}},
202-
{"zvfbfwma", {0, 8}},
201+
{"zvfbfmin", {1, 0}},
202+
{"zvfbfwma", {1, 0}},
203203
};
204204

205205
static void verifyTables() {

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@
238238
; RV32XCVMEM: .attribute 5, "rv32i2p1_xcvmem1p0"
239239
; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
240240
; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
241-
; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"
241+
; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
242242
; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
243243
; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
244244
; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
@@ -279,9 +279,9 @@
279279
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
280280
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
281281
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
282-
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
283-
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
284-
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
282+
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
283+
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
284+
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
285285
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
286286
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
287287

@@ -327,7 +327,7 @@
327327
; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
328328
; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
329329
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
330-
; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"
330+
; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
331331
; RV64XTHEADBA: .attribute 5, "rv64i2p1_xtheadba1p0"
332332
; RV64XTHEADBB: .attribute 5, "rv64i2p1_xtheadbb1p0"
333333
; RV64XTHEADBS: .attribute 5, "rv64i2p1_xtheadbs1p0"
@@ -372,9 +372,9 @@
372372
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
373373
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
374374
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
375-
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8"
376-
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
377-
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
375+
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
376+
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
377+
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
378378
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
379379
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
380380

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -273,14 +273,14 @@
273273
.attribute arch, "rv32i_ssaia1p0"
274274
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
275275

276-
.attribute arch, "rv32i_zfbfmin0p8"
277-
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
276+
.attribute arch, "rv32i_zfbfmin1p0"
277+
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
278278

279-
.attribute arch, "rv32i_zvfbfmin0p8"
280-
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0"
279+
.attribute arch, "rv32i_zvfbfmin1p0"
280+
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
281281

282-
.attribute arch, "rv32i_zvfbfwma0p8"
283-
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0"
282+
.attribute arch, "rv32i_zvfbfwma1p0"
283+
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
284284

285285
.attribute arch, "rv32izacas1p0"
286286
# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
@@ -313,4 +313,4 @@
313313
# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop0p1"
314314

315315
.attribute arch, "rv64i_xsfvfwmaccqqq"
316-
# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0_xsfvfwmaccqqq1p0"
316+
# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"

‎llvm/unittests/Support/RISCVISAInfoTest.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -788,11 +788,11 @@ Experimental extensions
788788
zicond 1.0
789789
zimop 0.1
790790
zacas 1.0
791-
zfbfmin 0.8
791+
zfbfmin 1.0
792792
zcmop 0.2
793793
ztso 0.1
794-
zvfbfmin 0.8
795-
zvfbfwma 0.8
794+
zvfbfmin 1.0
795+
zvfbfwma 1.0
796796
797797
Use -march to specify the target's extension.
798798
For example, clang -march=rv32i_v1p0)";

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