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early break if Ty isVector
1 parent 105fc1e commit 80a710e

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+9
-2
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1 file changed

+9
-2
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llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -317,8 +317,11 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
317317
OpdsMapping[0] = GPRValueMapping;
318318

319319
OpdsMapping[1] = GPRValueMapping;
320+
321+
if (Ty.isVector())
322+
break;
320323
// Use FPR64 for s64 loads on rv32.
321-
if (!Ty.isVector() && GPRSize == 32 && Size.getFixedValue() == 64) {
324+
if (GPRSize == 32 && Size.getFixedValue() == 64) {
322325
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
323326
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
324327
break;
@@ -345,8 +348,12 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
345348
OpdsMapping[0] = GPRValueMapping;
346349

347350
OpdsMapping[1] = GPRValueMapping;
351+
352+
if (Ty.isVector())
353+
break;
354+
348355
// Use FPR64 for s64 stores on rv32.
349-
if (!Ty.isVector() && GPRSize == 32 && Size.getFixedValue() == 64) {
356+
if (GPRSize == 32 && Size.getFixedValue() == 64) {
350357
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
351358
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
352359
break;

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