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AMDGPU: Add baseline test for vectorize of integer min/max
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  • llvm/test/Transforms/SLPVectorizer/AMDGPU

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‎llvm/test/Transforms/SLPVectorizer/AMDGPU/min_max.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX7 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX9 %s
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define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
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; GFX7-LABEL: @uadd_sat_v2i16(
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; GFX7-NEXT: bb:
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; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
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; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
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; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
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; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
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; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
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; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
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; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
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; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
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; GFX7-NEXT: ret <2 x i16> [[INS_1]]
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;
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; GFX8-LABEL: @uadd_sat_v2i16(
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; GFX8-NEXT: bb:
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; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX8-NEXT: ret <2 x i16> [[TMP0]]
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;
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; GFX9-LABEL: @uadd_sat_v2i16(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX9-NEXT: ret <2 x i16> [[TMP0]]
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;
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bb:
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%arg0.0 = extractelement <2 x i16> %arg0, i64 0
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%arg0.1 = extractelement <2 x i16> %arg0, i64 1
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%arg1.0 = extractelement <2 x i16> %arg1, i64 0
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%arg1.1 = extractelement <2 x i16> %arg1, i64 1
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%add.0 = call i16 @llvm.umin.i16(i16 %arg0.0, i16 %arg1.0)
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%add.1 = call i16 @llvm.umin.i16(i16 %arg0.1, i16 %arg1.1)
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%ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
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ret <2 x i16> %ins.1
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}
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define <2 x i16> @usub_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
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; GFX7-LABEL: @usub_sat_v2i16(
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; GFX7-NEXT: bb:
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; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
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; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
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; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
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; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
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; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.umax.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
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; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.umax.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
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; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
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; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
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; GFX7-NEXT: ret <2 x i16> [[INS_1]]
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;
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; GFX8-LABEL: @usub_sat_v2i16(
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; GFX8-NEXT: bb:
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; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX8-NEXT: ret <2 x i16> [[TMP0]]
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;
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; GFX9-LABEL: @usub_sat_v2i16(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX9-NEXT: ret <2 x i16> [[TMP0]]
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;
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bb:
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%arg0.0 = extractelement <2 x i16> %arg0, i64 0
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%arg0.1 = extractelement <2 x i16> %arg0, i64 1
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%arg1.0 = extractelement <2 x i16> %arg1, i64 0
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%arg1.1 = extractelement <2 x i16> %arg1, i64 1
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%add.0 = call i16 @llvm.umax.i16(i16 %arg0.0, i16 %arg1.0)
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%add.1 = call i16 @llvm.umax.i16(i16 %arg0.1, i16 %arg1.1)
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%ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
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ret <2 x i16> %ins.1
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}
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define <2 x i16> @sadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
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; GFX7-LABEL: @sadd_sat_v2i16(
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; GFX7-NEXT: bb:
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; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
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; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
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; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
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; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
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; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.smin.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
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; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.smin.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
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; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
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; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
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; GFX7-NEXT: ret <2 x i16> [[INS_1]]
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;
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; GFX8-LABEL: @sadd_sat_v2i16(
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; GFX8-NEXT: bb:
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; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX8-NEXT: ret <2 x i16> [[TMP0]]
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;
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; GFX9-LABEL: @sadd_sat_v2i16(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX9-NEXT: ret <2 x i16> [[TMP0]]
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;
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bb:
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%arg0.0 = extractelement <2 x i16> %arg0, i64 0
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%arg0.1 = extractelement <2 x i16> %arg0, i64 1
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%arg1.0 = extractelement <2 x i16> %arg1, i64 0
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%arg1.1 = extractelement <2 x i16> %arg1, i64 1
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%add.0 = call i16 @llvm.smin.i16(i16 %arg0.0, i16 %arg1.0)
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%add.1 = call i16 @llvm.smin.i16(i16 %arg0.1, i16 %arg1.1)
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%ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
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ret <2 x i16> %ins.1
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}
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define <2 x i16> @ssub_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
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; GFX7-LABEL: @ssub_sat_v2i16(
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; GFX7-NEXT: bb:
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; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
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; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
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; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
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; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
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; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.smax.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
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; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.smax.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
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; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
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; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
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; GFX7-NEXT: ret <2 x i16> [[INS_1]]
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;
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; GFX8-LABEL: @ssub_sat_v2i16(
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; GFX8-NEXT: bb:
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; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX8-NEXT: ret <2 x i16> [[TMP0]]
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;
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; GFX9-LABEL: @ssub_sat_v2i16(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
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; GFX9-NEXT: ret <2 x i16> [[TMP0]]
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;
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bb:
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%arg0.0 = extractelement <2 x i16> %arg0, i64 0
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%arg0.1 = extractelement <2 x i16> %arg0, i64 1
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%arg1.0 = extractelement <2 x i16> %arg1, i64 0
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%arg1.1 = extractelement <2 x i16> %arg1, i64 1
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%add.0 = call i16 @llvm.smax.i16(i16 %arg0.0, i16 %arg1.0)
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%add.1 = call i16 @llvm.smax.i16(i16 %arg0.1, i16 %arg1.1)
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%ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
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ret <2 x i16> %ins.1
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}
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define <2 x i32> @uadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
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; GCN-LABEL: @uadd_sat_v2i32(
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; GCN-NEXT: bb:
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; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
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; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
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; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
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; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
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; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.umin.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
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; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.umin.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
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; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
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; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
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; GCN-NEXT: ret <2 x i32> [[INS_1]]
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;
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bb:
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%arg0.0 = extractelement <2 x i32> %arg0, i64 0
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%arg0.1 = extractelement <2 x i32> %arg0, i64 1
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%arg1.0 = extractelement <2 x i32> %arg1, i64 0
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%arg1.1 = extractelement <2 x i32> %arg1, i64 1
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%add.0 = call i32 @llvm.umin.i32(i32 %arg0.0, i32 %arg1.0)
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%add.1 = call i32 @llvm.umin.i32(i32 %arg0.1, i32 %arg1.1)
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%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
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%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
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ret <2 x i32> %ins.1
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}
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define <2 x i32> @usub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
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; GCN-LABEL: @usub_sat_v2i32(
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; GCN-NEXT: bb:
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; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
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; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
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; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
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; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
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; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.umax.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
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; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.umax.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
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; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
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; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
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; GCN-NEXT: ret <2 x i32> [[INS_1]]
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;
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bb:
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%arg0.0 = extractelement <2 x i32> %arg0, i64 0
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%arg0.1 = extractelement <2 x i32> %arg0, i64 1
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%arg1.0 = extractelement <2 x i32> %arg1, i64 0
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%arg1.1 = extractelement <2 x i32> %arg1, i64 1
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%add.0 = call i32 @llvm.umax.i32(i32 %arg0.0, i32 %arg1.0)
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%add.1 = call i32 @llvm.umax.i32(i32 %arg0.1, i32 %arg1.1)
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%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
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%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
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ret <2 x i32> %ins.1
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}
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define <2 x i32> @sadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
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; GCN-LABEL: @sadd_sat_v2i32(
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; GCN-NEXT: bb:
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; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
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; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
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; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
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; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
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; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.smin.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
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; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.smin.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
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; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
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; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
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; GCN-NEXT: ret <2 x i32> [[INS_1]]
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;
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bb:
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%arg0.0 = extractelement <2 x i32> %arg0, i64 0
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%arg0.1 = extractelement <2 x i32> %arg0, i64 1
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%arg1.0 = extractelement <2 x i32> %arg1, i64 0
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%arg1.1 = extractelement <2 x i32> %arg1, i64 1
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%add.0 = call i32 @llvm.smin.i32(i32 %arg0.0, i32 %arg1.0)
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%add.1 = call i32 @llvm.smin.i32(i32 %arg0.1, i32 %arg1.1)
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%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
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%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
218+
ret <2 x i32> %ins.1
219+
}
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define <2 x i32> @ssub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
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; GCN-LABEL: @ssub_sat_v2i32(
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; GCN-NEXT: bb:
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; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
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; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
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; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
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; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
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; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.smax.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
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; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.smax.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
230+
; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
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; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
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; GCN-NEXT: ret <2 x i32> [[INS_1]]
233+
;
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bb:
235+
%arg0.0 = extractelement <2 x i32> %arg0, i64 0
236+
%arg0.1 = extractelement <2 x i32> %arg0, i64 1
237+
%arg1.0 = extractelement <2 x i32> %arg1, i64 0
238+
%arg1.1 = extractelement <2 x i32> %arg1, i64 1
239+
%add.0 = call i32 @llvm.smax.i32(i32 %arg0.0, i32 %arg1.0)
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%add.1 = call i32 @llvm.smax.i32(i32 %arg0.1, i32 %arg1.1)
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%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
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%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
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ret <2 x i32> %ins.1
244+
}
245+
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define <3 x i16> @uadd_sat_v3i16(<3 x i16> %arg0, <3 x i16> %arg1) {
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; GFX7-LABEL: @uadd_sat_v3i16(
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; GFX7-NEXT: bb:
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; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 0
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; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <3 x i16> [[ARG0]], i64 1
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; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0]], i64 2
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; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 0
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; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <3 x i16> [[ARG1]], i64 1
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; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1]], i64 2
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; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
256+
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
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; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
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; GFX7-NEXT: [[INS_0:%.*]] = insertelement <3 x i16> poison, i16 [[ADD_0]], i64 0
259+
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
260+
; GFX7-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
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; GFX7-NEXT: ret <3 x i16> [[INS_2]]
262+
;
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; GFX8-LABEL: @uadd_sat_v3i16(
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; GFX8-NEXT: bb:
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; GFX8-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 2
266+
; GFX8-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 2
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; GFX8-NEXT: [[TMP0:%.*]] = call <3 x i16> @llvm.umin.v3i16(<3 x i16> [[ARG0]], <3 x i16> [[ARG1]])
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; GFX8-NEXT: [[ADD_2:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
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; GFX8-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[TMP0]], i16 [[ADD_2]], i64 2
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; GFX8-NEXT: ret <3 x i16> [[INS_2]]
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;
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; GFX9-LABEL: @uadd_sat_v3i16(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 2
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; GFX9-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 2
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; GFX9-NEXT: [[TMP0:%.*]] = call <3 x i16> @llvm.umin.v3i16(<3 x i16> [[ARG0]], <3 x i16> [[ARG1]])
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; GFX9-NEXT: [[ADD_2:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
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; GFX9-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[TMP0]], i16 [[ADD_2]], i64 2
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; GFX9-NEXT: ret <3 x i16> [[INS_2]]
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;
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bb:
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%arg0.0 = extractelement <3 x i16> %arg0, i64 0
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%arg0.1 = extractelement <3 x i16> %arg0, i64 1
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%arg0.2 = extractelement <3 x i16> %arg0, i64 2
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%arg1.0 = extractelement <3 x i16> %arg1, i64 0
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%arg1.1 = extractelement <3 x i16> %arg1, i64 1
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%arg1.2 = extractelement <3 x i16> %arg1, i64 2
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%add.0 = call i16 @llvm.umin.i16(i16 %arg0.0, i16 %arg1.0)
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%add.1 = call i16 @llvm.umin.i16(i16 %arg0.1, i16 %arg1.1)
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%add.2 = call i16 @llvm.umin.i16(i16 %arg0.2, i16 %arg1.2)
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%ins.0 = insertelement <3 x i16> undef, i16 %add.0, i64 0
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%ins.1 = insertelement <3 x i16> %ins.0, i16 %add.1, i64 1
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%ins.2 = insertelement <3 x i16> %ins.1, i16 %add.2, i64 2
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ret <3 x i16> %ins.2
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}
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define <4 x i16> @uadd_sat_v4i16(<4 x i16> %arg0, <4 x i16> %arg1) {
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; GFX7-LABEL: @uadd_sat_v4i16(
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; GFX7-NEXT: bb:
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; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <4 x i16> [[ARG0:%.*]], i64 0
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; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <4 x i16> [[ARG0]], i64 1
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; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i16> [[ARG0]], i64 2
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; GFX7-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i16> [[ARG0]], i64 3
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; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 0
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; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i16> [[ARG1]], i64 1
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; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1]], i64 2
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; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3
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; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
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; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
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; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
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; GFX7-NEXT: [[ADD_3:%.*]] = call i16 @llvm.umin.i16(i16 [[ARG0_3]], i16 [[ARG1_3]])
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; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i16> poison, i16 [[ADD_0]], i64 0
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; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
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; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
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; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3
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; GFX7-NEXT: ret <4 x i16> [[INS_3]]
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;
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; GFX8-LABEL: @uadd_sat_v4i16(
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; GFX8-NEXT: bb:
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; GFX8-NEXT: [[TMP0:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[ARG0:%.*]], <4 x i16> [[ARG1:%.*]])
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; GFX8-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[ARG0]], <4 x i16> [[ARG1]])
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; GFX8-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
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; GFX8-NEXT: [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; GFX8-NEXT: [[INS_31:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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; GFX8-NEXT: ret <4 x i16> [[INS_31]]
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;
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; GFX9-LABEL: @uadd_sat_v4i16(
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; GFX9-NEXT: bb:
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; GFX9-NEXT: [[TMP0:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[ARG0:%.*]], <4 x i16> [[ARG1:%.*]])
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; GFX9-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[ARG0]], <4 x i16> [[ARG1]])
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; GFX9-NEXT: [[TMP2:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>
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; GFX9-NEXT: [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; GFX9-NEXT: [[INS_31:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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; GFX9-NEXT: ret <4 x i16> [[INS_31]]
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;
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bb:
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%arg0.0 = extractelement <4 x i16> %arg0, i64 0
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%arg0.1 = extractelement <4 x i16> %arg0, i64 1
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%arg0.2 = extractelement <4 x i16> %arg0, i64 2
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%arg0.3 = extractelement <4 x i16> %arg0, i64 3
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%arg1.0 = extractelement <4 x i16> %arg1, i64 0
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%arg1.1 = extractelement <4 x i16> %arg1, i64 1
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%arg1.2 = extractelement <4 x i16> %arg1, i64 2
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%arg1.3 = extractelement <4 x i16> %arg1, i64 3
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%add.0 = call i16 @llvm.umin.i16(i16 %arg0.0, i16 %arg1.0)
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%add.1 = call i16 @llvm.umin.i16(i16 %arg0.1, i16 %arg1.1)
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%add.2 = call i16 @llvm.umin.i16(i16 %arg0.2, i16 %arg1.2)
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%add.3 = call i16 @llvm.umin.i16(i16 %arg0.3, i16 %arg1.3)
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%ins.0 = insertelement <4 x i16> undef, i16 %add.0, i64 0
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%ins.1 = insertelement <4 x i16> %ins.0, i16 %add.1, i64 1
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%ins.2 = insertelement <4 x i16> %ins.1, i16 %add.2, i64 2
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%ins.3 = insertelement <4 x i16> %ins.2, i16 %add.3, i64 3
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ret <4 x i16> %ins.3
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}
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declare i16 @llvm.umin.i16(i16, i16) #0
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declare i16 @llvm.umax.i16(i16, i16) #0
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declare i16 @llvm.smin.i16(i16, i16) #0
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declare i16 @llvm.smax.i16(i16, i16) #0
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declare i32 @llvm.umin.i32(i32, i32) #0
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declare i32 @llvm.umax.i32(i32, i32) #0
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declare i32 @llvm.smin.i32(i32, i32) #0
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declare i32 @llvm.smax.i32(i32, i32) #0
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attributes #0 = { nounwind readnone speculatable willreturn }

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