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[RISCV][NFC] refactoring
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2 files changed

+83
-80
lines changed

2 files changed

+83
-80
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 78 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -27,83 +27,45 @@
2727

2828
using namespace llvm;
2929

30-
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
31-
return RISCV::VRRegClass.contains(BaseReg) ? 1
32-
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
33-
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
34-
: 8;
35-
}
36-
37-
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
38-
const Register &Reg) {
39-
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
40-
// If it's not a grouped vector register, it doesn't have subregister, so
41-
// the base register is just itself.
42-
if (BaseReg == RISCV::NoRegister)
43-
BaseReg = Reg;
44-
return BaseReg;
45-
}
46-
4730
namespace {
4831

49-
struct CFIRestoreRegisterEmitter {
50-
CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
51-
52-
void emit(MachineFunction &MF, MachineBasicBlock &MBB,
53-
MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
54-
const RISCVInstrInfo &TII, const DebugLoc &DL,
55-
const CalleeSavedInfo &CS) const {
56-
Register Reg = CS.getReg();
57-
unsigned CFIIndex = MF.addFrameInst(
58-
MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
59-
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
60-
.addCFIIndex(CFIIndex)
61-
.setMIFlag(MachineInstr::FrameDestroy);
62-
}
63-
};
64-
65-
class CFIStoreRegisterEmitter {
66-
MachineFrameInfo &MFI;
32+
class CFISaveRegisterEmitter {
33+
MachineFunction &m_MF;
34+
MachineFrameInfo &m_MFI;
6735

6836
public:
69-
CFIStoreRegisterEmitter(MachineFunction &MF, const RISCVSubtarget &)
70-
: MFI{MF.getFrameInfo()} {};
37+
CFISaveRegisterEmitter(MachineFunction &MF)
38+
: m_MF{MF}, m_MFI{MF.getFrameInfo()} {};
7139

72-
void emit(MachineFunction &MF, MachineBasicBlock &MBB,
73-
MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
74-
const RISCVInstrInfo &TII, const DebugLoc &DL,
75-
const CalleeSavedInfo &CS) const {
40+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
41+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
42+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
7643
int FrameIdx = CS.getFrameIdx();
77-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
44+
int64_t Offset = m_MFI.getObjectOffset(FrameIdx);
7845
Register Reg = CS.getReg();
79-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
46+
unsigned CFIIndex = m_MF.addFrameInst(MCCFIInstruction::createOffset(
8047
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
8148
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
8249
.addCFIIndex(CFIIndex)
8350
.setMIFlag(MachineInstr::FrameSetup);
8451
}
8552
};
8653

87-
class CFIRestoreRVVRegisterEmitter {
88-
const llvm::RISCVRegisterInfo *TRI;
54+
class CFIRestoreRegisterEmitter {
55+
MachineFunction &m_MF;
8956

9057
public:
91-
CFIRestoreRVVRegisterEmitter(MachineFunction &, const RISCVSubtarget &STI)
92-
: TRI{STI.getRegisterInfo()} {};
93-
94-
void emit(MachineFunction &MF, MachineBasicBlock &MBB,
95-
MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
96-
const RISCVInstrInfo &TII, const DebugLoc &DL,
97-
const CalleeSavedInfo &CS) const {
98-
MCRegister BaseReg = getRVVBaseRegister(*TRI, CS.getReg());
99-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
100-
for (unsigned i = 0; i < NumRegs; ++i) {
101-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
102-
nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
103-
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
104-
.addCFIIndex(CFIIndex)
105-
.setMIFlag(MachineInstr::FrameDestroy);
106-
}
58+
CFIRestoreRegisterEmitter(MachineFunction &MF) : m_MF{MF} {};
59+
60+
void emit(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
61+
const RISCVRegisterInfo &RI, const RISCVInstrInfo &TII,
62+
const DebugLoc &DL, const CalleeSavedInfo &CS) const {
63+
Register Reg = CS.getReg();
64+
unsigned CFIIndex = m_MF.addFrameInst(
65+
MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
66+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
67+
.addCFIIndex(CFIIndex)
68+
.setMIFlag(MachineInstr::FrameDestroy);
10769
}
10870
};
10971

@@ -118,9 +80,9 @@ void RISCVFrameLowering::emitCFIForCSI(
11880
const RISCVInstrInfo *TII = STI.getInstrInfo();
11981
DebugLoc DL = MBB.findDebugLoc(MBBI);
12082

121-
Emitter E{*MF, STI};
83+
Emitter E{*MF};
12284
for (const auto &CS : CSI)
123-
E.emit(*MF, MBB, MBBI, *RI, *TII, DL, CS);
85+
E.emit(MBB, MBBI, *RI, *TII, DL, CS);
12486
}
12587

12688
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
@@ -514,18 +476,18 @@ getPushOrLibCallsSavedInfo(const MachineFunction &MF,
514476
const std::vector<CalleeSavedInfo> &CSI) {
515477
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
516478

517-
SmallVector<CalleeSavedInfo, 8> PushPopOrLibCallsCSI;
479+
SmallVector<CalleeSavedInfo, 8> PushOrLibCallsCSI;
518480
if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
519-
return PushPopOrLibCallsCSI;
481+
return PushOrLibCallsCSI;
520482

521-
for (auto &CS : CSI) {
483+
for (const auto &CS : CSI) {
522484
const auto *FII = llvm::find_if(
523485
FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); });
524486
if (FII != std::end(FixedCSRFIMap))
525-
PushPopOrLibCallsCSI.push_back(CS);
487+
PushOrLibCallsCSI.push_back(CS);
526488
}
527489

528-
return PushPopOrLibCallsCSI;
490+
return PushOrLibCallsCSI;
529491
}
530492

531493
void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
@@ -706,8 +668,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
706668
.addCFIIndex(CFIIndex)
707669
.setMIFlag(MachineInstr::FrameSetup);
708670

709-
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
710-
getPushOrLibCallsSavedInfo(MF, CSI));
671+
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI,
672+
getPushOrLibCallsSavedInfo(MF, CSI));
711673
}
712674

713675
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -739,7 +701,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
739701
// stack space. Align the stack size down to a multiple of 16. This is
740702
// needed for RVE.
741703
// FIXME: Can we increase the stack size to a multiple of 16 instead?
742-
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
704+
uint64_t Spimm = std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
743705
FirstFrameSetup->getOperand(1).setImm(Spimm);
744706
StackSize -= Spimm;
745707

@@ -749,8 +711,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
749711
.addCFIIndex(CFIIndex)
750712
.setMIFlag(MachineInstr::FrameSetup);
751713

752-
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
753-
getPushOrLibCallsSavedInfo(MF, CSI));
714+
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI,
715+
getPushOrLibCallsSavedInfo(MF, CSI));
754716
}
755717

756718
if (StackSize != 0) {
@@ -777,7 +739,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
777739

778740
// Iterate over list of callee-saved registers and emit .cfi_offset
779741
// directives.
780-
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
742+
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
781743

782744
// Generate new FP.
783745
if (hasFP(MF)) {
@@ -962,8 +924,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
962924
.setMIFlag(MachineInstr::FrameDestroy);
963925
}
964926

965-
emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy,
966-
getRVVCalleeSavedInfo(MF, CSI));
927+
emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
967928
}
968929

969930
if (FirstSPAdjustAmount) {
@@ -1751,6 +1712,23 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
17511712
return true;
17521713
}
17531714

1715+
static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg) {
1716+
return RISCV::VRRegClass.contains(BaseReg) ? 1
1717+
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
1718+
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
1719+
: 8;
1720+
}
1721+
1722+
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
1723+
const Register &Reg) {
1724+
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
1725+
// If it's not a grouped vector register, it doesn't have subregister, so
1726+
// the base register is just itself.
1727+
if (BaseReg == RISCV::NoRegister)
1728+
BaseReg = Reg;
1729+
return BaseReg;
1730+
}
1731+
17541732
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17551733
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
17561734
MachineFunction *MF = MBB.getParent();
@@ -1777,7 +1755,7 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17771755
// Insert the spill to the stack frame.
17781756
int FI = CS.getFrameIdx();
17791757
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1780-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
1758+
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
17811759
for (unsigned i = 0; i < NumRegs; ++i) {
17821760
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
17831761
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
@@ -1788,6 +1766,29 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17881766
}
17891767
}
17901768

1769+
void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1770+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
1771+
MachineFunction *MF = MBB.getParent();
1772+
const MachineFrameInfo &MFI = MF->getFrameInfo();
1773+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
1774+
const TargetInstrInfo &TII = *STI.getInstrInfo();
1775+
const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
1776+
DebugLoc DL = MBB.findDebugLoc(MI);
1777+
1778+
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1779+
for (auto &CS : RVVCSI) {
1780+
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1781+
unsigned NumRegs = getCalleeSavedRVVNumRegs(CS.getReg());
1782+
for (unsigned i = 0; i < NumRegs; ++i) {
1783+
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
1784+
nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
1785+
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1786+
.addCFIIndex(CFIIndex)
1787+
.setMIFlag(MachineInstr::FrameDestroy);
1788+
}
1789+
}
1790+
}
1791+
17911792
bool RISCVFrameLowering::restoreCalleeSavedRegisters(
17921793
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
17931794
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -91,12 +91,14 @@ class RISCVFrameLowering : public TargetFrameLowering {
9191
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
9292
MachineBasicBlock::iterator MI,
9393
bool HasFP) const;
94-
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
95-
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
96-
uint64_t &StackSize, int64_t CFAOffset) const;
94+
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
95+
MachineBasicBlock::iterator MI) const;
9796
template <typename Emitter>
9897
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
9998
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
99+
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
100+
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
101+
uint64_t &StackSize, int64_t CFAOffset) const;
100102

101103
std::pair<int64_t, Align>
102104
assignRVVStackObjectOffsets(MachineFunction &MF) const;

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