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[ASAN][AMDGPU] NFC. Improve instrumentation tests. (#73919)
* Added 128 bit wide operation tests (fast path check). * Added test for recovery mode. Upcoming patch #72247.
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‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll

Lines changed: 72 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,11 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
22
; RUN: opt < %s -passes=asan -S | FileCheck %s
3+
; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV
34
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
45
target triple = "amdgcn-amd-amdhsa"
56

67
@x = addrspace(4) global [2 x i32] zeroinitializer, align 4
8+
@x8 = addrspace(4) global [2 x i64] zeroinitializer, align 8
79

810
define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
911
; CHECK-LABEL: define protected amdgpu_kernel void @constant_load(
@@ -16,7 +18,7 @@ define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
1618
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
1719
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
1820
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
19-
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF1:![0-9]+]]
21+
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF2:![0-9]+]]
2022
; CHECK: 6:
2123
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
2224
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
@@ -30,9 +32,77 @@ define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
3032
; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4
3133
; CHECK-NEXT: ret void
3234
;
35+
; RECOV-LABEL: define protected amdgpu_kernel void @constant_load(
36+
; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
37+
; RECOV-NEXT: entry:
38+
; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]]
39+
; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
40+
; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
41+
; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
42+
; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
43+
; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
44+
; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
45+
; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP13:%.*]], !prof [[PROF2:![0-9]+]]
46+
; RECOV: 6:
47+
; RECOV-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
48+
; RECOV-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
49+
; RECOV-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
50+
; RECOV-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
51+
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
52+
; RECOV: 11:
53+
; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP0]]) #[[ATTR3:[0-9]+]]
54+
; RECOV-NEXT: br label [[TMP12]]
55+
; RECOV: 12:
56+
; RECOV-NEXT: br label [[TMP13]]
57+
; RECOV: 13:
58+
; RECOV-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4
59+
; RECOV-NEXT: ret void
60+
;
3361
entry:
34-
3562
%a = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 %i
3663
%q = load i32, ptr addrspace(4) %a, align 4
3764
ret void
3865
}
66+
67+
define protected amdgpu_kernel void @constant_load_8(i64 %i) sanitize_address {
68+
; CHECK-LABEL: define protected amdgpu_kernel void @constant_load_8(
69+
; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0]] {
70+
; CHECK-NEXT: entry:
71+
; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]]
72+
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
73+
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
74+
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
75+
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
76+
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
77+
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
78+
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]]
79+
; CHECK: 6:
80+
; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP0]]) #[[ATTR3]]
81+
; CHECK-NEXT: unreachable
82+
; CHECK: 7:
83+
; CHECK-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8
84+
; CHECK-NEXT: ret void
85+
;
86+
; RECOV-LABEL: define protected amdgpu_kernel void @constant_load_8(
87+
; RECOV-SAME: i64 [[I:%.*]]) #[[ATTR0]] {
88+
; RECOV-NEXT: entry:
89+
; RECOV-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 [[I]]
90+
; RECOV-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
91+
; RECOV-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
92+
; RECOV-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
93+
; RECOV-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
94+
; RECOV-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
95+
; RECOV-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
96+
; RECOV-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]]
97+
; RECOV: 6:
98+
; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP0]]) #[[ATTR3]]
99+
; RECOV-NEXT: br label [[TMP7]]
100+
; RECOV: 7:
101+
; RECOV-NEXT: [[Q:%.*]] = load i64, ptr addrspace(4) [[A]], align 8
102+
; RECOV-NEXT: ret void
103+
;
104+
entry:
105+
%a = getelementptr inbounds [2 x i64], ptr addrspace(4) @x8, i64 0, i64 %i
106+
%q = load i64, ptr addrspace(4) %a, align 8
107+
ret void
108+
}

‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
22
; RUN: opt < %s -passes=asan -S | FileCheck %s
3+
; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV
34
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
45
target triple = "amdgcn-amd-amdhsa"
56

@@ -36,6 +37,40 @@ define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i)
3637
; CHECK-NEXT: store i32 0, ptr [[Q]], align 4
3738
; CHECK-NEXT: ret void
3839
;
40+
; RECOV-LABEL: define protected amdgpu_kernel void @generic_store(
41+
; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
42+
; RECOV-NEXT: entry:
43+
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
44+
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
45+
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
46+
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
47+
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
48+
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP19:%.*]]
49+
; RECOV: 4:
50+
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
51+
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
52+
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
53+
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
54+
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
55+
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
56+
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF0:![0-9]+]]
57+
; RECOV: 11:
58+
; RECOV-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7
59+
; RECOV-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3
60+
; RECOV-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
61+
; RECOV-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
62+
; RECOV-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17:%.*]]
63+
; RECOV: 16:
64+
; RECOV-NEXT: call void @__asan_report_store4_noabort(i64 [[TMP5]]) #[[ATTR3:[0-9]+]]
65+
; RECOV-NEXT: br label [[TMP17]]
66+
; RECOV: 17:
67+
; RECOV-NEXT: br label [[TMP18]]
68+
; RECOV: 18:
69+
; RECOV-NEXT: br label [[TMP19]]
70+
; RECOV: 19:
71+
; RECOV-NEXT: store i32 0, ptr [[Q]], align 4
72+
; RECOV-NEXT: ret void
73+
;
3974
entry:
4075

4176
%q = addrspacecast ptr addrspace(1) %p to ptr
@@ -76,9 +111,161 @@ define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) s
76111
; CHECK-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4
77112
; CHECK-NEXT: ret void
78113
;
114+
; RECOV-LABEL: define protected amdgpu_kernel void @generic_load(
115+
; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
116+
; RECOV-NEXT: entry:
117+
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
118+
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
119+
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
120+
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
121+
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
122+
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP19:%.*]]
123+
; RECOV: 4:
124+
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
125+
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
126+
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
127+
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
128+
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
129+
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
130+
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP18:%.*]], !prof [[PROF0]]
131+
; RECOV: 11:
132+
; RECOV-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7
133+
; RECOV-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3
134+
; RECOV-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
135+
; RECOV-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
136+
; RECOV-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17:%.*]]
137+
; RECOV: 16:
138+
; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP5]]) #[[ATTR3]]
139+
; RECOV-NEXT: br label [[TMP17]]
140+
; RECOV: 17:
141+
; RECOV-NEXT: br label [[TMP18]]
142+
; RECOV: 18:
143+
; RECOV-NEXT: br label [[TMP19]]
144+
; RECOV: 19:
145+
; RECOV-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4
146+
; RECOV-NEXT: ret void
147+
;
79148
entry:
80149

81150
%q = addrspacecast ptr addrspace(1) %p to ptr
82151
%r = load i32, ptr %q, align 4
83152
ret void
84153
}
154+
155+
define protected amdgpu_kernel void @generic_store_8(ptr addrspace(1) %p) sanitize_address {
156+
; CHECK-LABEL: define protected amdgpu_kernel void @generic_store_8(
157+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
158+
; CHECK-NEXT: entry:
159+
; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
160+
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
161+
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
162+
; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
163+
; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
164+
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
165+
; CHECK: 4:
166+
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
167+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
168+
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
169+
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
170+
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
171+
; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
172+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
173+
; CHECK: 11:
174+
; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP5]]) #[[ATTR3]]
175+
; CHECK-NEXT: unreachable
176+
; CHECK: 12:
177+
; CHECK-NEXT: br label [[TMP13]]
178+
; CHECK: 13:
179+
; CHECK-NEXT: store i64 0, ptr [[Q]], align 8
180+
; CHECK-NEXT: ret void
181+
;
182+
; RECOV-LABEL: define protected amdgpu_kernel void @generic_store_8(
183+
; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
184+
; RECOV-NEXT: entry:
185+
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
186+
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
187+
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
188+
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
189+
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
190+
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
191+
; RECOV: 4:
192+
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
193+
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
194+
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
195+
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
196+
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
197+
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
198+
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
199+
; RECOV: 11:
200+
; RECOV-NEXT: call void @__asan_report_store8_noabort(i64 [[TMP5]]) #[[ATTR3]]
201+
; RECOV-NEXT: br label [[TMP12]]
202+
; RECOV: 12:
203+
; RECOV-NEXT: br label [[TMP13]]
204+
; RECOV: 13:
205+
; RECOV-NEXT: store i64 0, ptr [[Q]], align 8
206+
; RECOV-NEXT: ret void
207+
;
208+
entry:
209+
%q = addrspacecast ptr addrspace(1) %p to ptr
210+
store i64 0, ptr %q, align 8
211+
ret void
212+
}
213+
214+
define protected amdgpu_kernel void @generic_load_8(ptr addrspace(1) %p) sanitize_address {
215+
; CHECK-LABEL: define protected amdgpu_kernel void @generic_load_8(
216+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
217+
; CHECK-NEXT: entry:
218+
; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
219+
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
220+
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
221+
; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
222+
; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
223+
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
224+
; CHECK: 4:
225+
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
226+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
227+
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
228+
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
229+
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
230+
; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
231+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
232+
; CHECK: 11:
233+
; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP5]]) #[[ATTR3]]
234+
; CHECK-NEXT: unreachable
235+
; CHECK: 12:
236+
; CHECK-NEXT: br label [[TMP13]]
237+
; CHECK: 13:
238+
; CHECK-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8
239+
; CHECK-NEXT: ret void
240+
;
241+
; RECOV-LABEL: define protected amdgpu_kernel void @generic_load_8(
242+
; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {
243+
; RECOV-NEXT: entry:
244+
; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
245+
; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
246+
; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
247+
; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
248+
; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
249+
; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP13:%.*]]
250+
; RECOV: 4:
251+
; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
252+
; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
253+
; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
254+
; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
255+
; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
256+
; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
257+
; RECOV-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12:%.*]]
258+
; RECOV: 11:
259+
; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP5]]) #[[ATTR3]]
260+
; RECOV-NEXT: br label [[TMP12]]
261+
; RECOV: 12:
262+
; RECOV-NEXT: br label [[TMP13]]
263+
; RECOV: 13:
264+
; RECOV-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8
265+
; RECOV-NEXT: ret void
266+
;
267+
entry:
268+
%q = addrspacecast ptr addrspace(1) %p to ptr
269+
%r = load i64, ptr %q, align 8
270+
ret void
271+
}

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