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[AArch64][GlobalISel] Pre-Commit Test Update for Legalize G_ABS Large Vector
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‎llvm/test/CodeGen/AArch64/abs.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; CHECK-GI: warning: Instruction selection used fallback path for abs_v4i8
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v32i8
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v2i16
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v16i16
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v8i32
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v4i64
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v3i8
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v7i8
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v3i16
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v7i16
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_v3i32
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; ===== Legal Scalars =====
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define i8 @abs_i8(i8 %a){
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; CHECK-SD-LABEL: abs_i8:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sxtb w8, w0
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; CHECK-SD-NEXT: cmp w8, #0
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; CHECK-SD-NEXT: cneg w0, w8, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs_i8:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: sxtb w8, w0
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; CHECK-GI-NEXT: asr w8, w8, #7
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; CHECK-GI-NEXT: add w9, w0, w8
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; CHECK-GI-NEXT: eor w0, w9, w8
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; CHECK-GI-NEXT: ret
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entry:
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%res = call i8 @llvm.abs.i8(i8 %a, i1 0)
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ret i8 %res
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}
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declare i8 @llvm.abs.i8(i8, i1)
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define i16 @abs_i16(i16 %a){
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; CHECK-SD-LABEL: abs_i16:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sxth w8, w0
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; CHECK-SD-NEXT: cmp w8, #0
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; CHECK-SD-NEXT: cneg w0, w8, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs_i16:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: sxth w8, w0
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; CHECK-GI-NEXT: asr w8, w8, #15
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; CHECK-GI-NEXT: add w9, w0, w8
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; CHECK-GI-NEXT: eor w0, w9, w8
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; CHECK-GI-NEXT: ret
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entry:
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%res = call i16 @llvm.abs.i16(i16 %a, i1 0)
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ret i16 %res
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}
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declare i16 @llvm.abs.i16(i16, i1)
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define i32 @abs_i32(i32 %a){
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; CHECK-SD-LABEL: abs_i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: cneg w0, w0, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs_i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: asr w8, w0, #31
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; CHECK-GI-NEXT: add w9, w0, w8
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; CHECK-GI-NEXT: eor w0, w9, w8
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; CHECK-GI-NEXT: ret
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entry:
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%res = call i32 @llvm.abs.i32(i32 %a, i1 0)
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ret i32 %res
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}
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declare i32 @llvm.abs.i32(i32, i1)
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define i64 @abs_i64(i64 %a){
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; CHECK-SD-LABEL: abs_i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cneg x0, x0, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs_i64:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: asr x8, x0, #63
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; CHECK-GI-NEXT: add x9, x0, x8
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; CHECK-GI-NEXT: eor x0, x9, x8
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; CHECK-GI-NEXT: ret
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entry:
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%res = call i64 @llvm.abs.i64(i64 %a, i1 0)
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ret i64 %res
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}
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declare i64 @llvm.abs.i64(i64, i1)
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define i128 @abs_i128(i128 %a){
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; CHECK-SD-LABEL: abs_i128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: asr x8, x1, #63
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; CHECK-SD-NEXT: eor x9, x0, x8
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; CHECK-SD-NEXT: eor x10, x1, x8
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; CHECK-SD-NEXT: subs x0, x9, x8
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; CHECK-SD-NEXT: sbc x1, x10, x8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs_i128:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: asr x8, x1, #63
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; CHECK-GI-NEXT: adds x9, x0, x8
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; CHECK-GI-NEXT: adc x10, x1, x8
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; CHECK-GI-NEXT: eor x0, x9, x8
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; CHECK-GI-NEXT: eor x1, x10, x8
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; CHECK-GI-NEXT: ret
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entry:
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%res = call i128 @llvm.abs.i128(i128 %a, i1 0)
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ret i128 %res
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}
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declare i128 @llvm.abs.i128(i128, i1)
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; ===== Legal Vector Types =====
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define <8 x i8> @abs_v8i8(<8 x i8> %a){
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; CHECK-LABEL: abs_v8i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.8b, v0.8b
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i8> @llvm.abs.v8i8(<8 x i8> %a, i1 0)
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ret <8 x i8> %res
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}
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declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)
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define <16 x i8> @abs_v16i8(<16 x i8> %a){
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; CHECK-LABEL: abs_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.16b, v0.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 0)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
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define <4 x i16> @abs_v4i16(<4 x i16> %a){
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; CHECK-LABEL: abs_v4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.4h, v0.4h
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %a, i1 0)
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ret <4 x i16> %res
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}
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declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)
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define <8 x i16> @abs_v8i16(<8 x i16> %a){
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; CHECK-LABEL: abs_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.8h, v0.8h
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 0)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
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define <2 x i32> @abs_v2i32(<2 x i32> %a){
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; CHECK-LABEL: abs_v2i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.2s, v0.2s
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 0)
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ret <2 x i32> %res
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}
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declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
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define <4 x i32> @abs_v4i32(<4 x i32> %a){
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; CHECK-LABEL: abs_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.4s, v0.4s
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 0)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
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define <2 x i64> @abs_v2i64(<2 x i64> %a){
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; CHECK-LABEL: abs_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.2d, v0.2d
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 0)
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
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; ===== Smaller/Larger Width Vectors with Legal Element Sizes =====
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define <4 x i8> @abs_v4i8(<4 x i8> %a){
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; CHECK-LABEL: abs_v4i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: abs v0.4h, v0.4h
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i8> @llvm.abs.v4i8(<4 x i8> %a, i1 0)
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ret <4 x i8> %res
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}
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declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
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define <32 x i8> @abs_v32i8(<32 x i8> %a){
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; CHECK-LABEL: abs_v32i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.16b, v0.16b
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; CHECK-NEXT: abs v1.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%res = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 0)
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ret <32 x i8> %res
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}
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declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)
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define <2 x i16> @abs_v2i16(<2 x i16> %a){
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; CHECK-LABEL: abs_v2i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: shl v0.2s, v0.2s, #16
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; CHECK-NEXT: sshr v0.2s, v0.2s, #16
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; CHECK-NEXT: abs v0.2s, v0.2s
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %a, i1 0)
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ret <2 x i16> %res
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}
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declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
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define <16 x i16> @abs_v16i16(<16 x i16> %a){
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; CHECK-LABEL: abs_v16i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.8h, v0.8h
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; CHECK-NEXT: abs v1.8h, v1.8h
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 0)
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ret <16 x i16> %res
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}
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declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)
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define <1 x i32> @abs_v1i32(<1 x i32> %a){
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; CHECK-SD-LABEL: abs_v1i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: abs v0.2s, v0.2s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs_v1i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fmov x8, d0
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; CHECK-GI-NEXT: asr w9, w8, #31
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; CHECK-GI-NEXT: add w8, w8, w9
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; CHECK-GI-NEXT: eor w8, w8, w9
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; CHECK-GI-NEXT: fmov s0, w8
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; CHECK-GI-NEXT: mov v0.s[1], w8
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-GI-NEXT: ret
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entry:
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%res = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 0)
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ret <1 x i32> %res
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}
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declare <1 x i32> @llvm.abs.v1i32(<1 x i32>, i1)
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define <8 x i32> @abs_v8i32(<8 x i32> %a){
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; CHECK-LABEL: abs_v8i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.4s, v0.4s
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; CHECK-NEXT: abs v1.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 0)
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
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define <4 x i64> @abs_v4i64(<4 x i64> %a){
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; CHECK-LABEL: abs_v4i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.2d, v0.2d
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; CHECK-NEXT: abs v1.2d, v1.2d
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 0)
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
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; ===== Vectors with Non-Pow 2 Widths =====
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define <3 x i8> @abs_v3i8(<3 x i8> %a){
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; CHECK-LABEL: abs_v3i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: mov v0.h[1], w1
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; CHECK-NEXT: mov v0.h[2], w2
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; CHECK-NEXT: shl v0.4h, v0.4h, #8
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; CHECK-NEXT: sshr v0.4h, v0.4h, #8
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; CHECK-NEXT: abs v0.4h, v0.4h
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: umov w1, v0.h[1]
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; CHECK-NEXT: umov w2, v0.h[2]
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; CHECK-NEXT: ret
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entry:
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%res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %a, i1 0)
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ret <3 x i8> %res
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}
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declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)
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define <7 x i8> @abs_v7i8(<7 x i8> %a){
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; CHECK-LABEL: abs_v7i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.8b, v0.8b
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; CHECK-NEXT: ret
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entry:
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%res = call <7 x i8> @llvm.abs.v7i8(<7 x i8> %a, i1 0)
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ret <7 x i8> %res
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}
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declare <7 x i8> @llvm.abs.v7i8(<7 x i8>, i1)
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define <3 x i16> @abs_v3i16(<3 x i16> %a){
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; CHECK-LABEL: abs_v3i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.4h, v0.4h
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; CHECK-NEXT: ret
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entry:
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%res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %a, i1 0)
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ret <3 x i16> %res
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}
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declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
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define <7 x i16> @abs_v7i16(<7 x i16> %a){
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; CHECK-LABEL: abs_v7i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.8h, v0.8h
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; CHECK-NEXT: ret
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entry:
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%res = call <7 x i16> @llvm.abs.v7i16(<7 x i16> %a, i1 0)
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ret <7 x i16> %res
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}
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declare <7 x i16> @llvm.abs.v7i16(<7 x i16>, i1)
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define <3 x i32> @abs_v3i32(<3 x i32> %a){
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; CHECK-LABEL: abs_v3i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: abs v0.4s, v0.4s
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; CHECK-NEXT: ret
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entry:
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%res = call <3 x i32> @llvm.abs.v3i32(<3 x i32> %a, i1 0)
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ret <3 x i32> %res
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}
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declare <3 x i32> @llvm.abs.v3i32(<3 x i32>, i1)

‎llvm/test/CodeGen/AArch64/vecreduce-add.ll

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,13 @@
44
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-BASE
55
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=2 %s -o - -mattr=+dotprod 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-DOT
66

7-
; CHECK-GI-BASE: warning: Instruction selection used fallback path for full
7+
; CHECK-GI-BASE: warning: Instruction selection used fallback path for test_udot_v24i8
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; CHECK-GI-BASE-NEXT: warning: Instruction selection used fallback path for test_udot_v48i8
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; CHECK-GI-BASE-NEXT: warning: Instruction selection used fallback path for test_sdot_v24i8
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; CHECK-GI-BASE-NEXT: warning: Instruction selection used fallback path for test_sdot_v48i8
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; CHECK-GI-BASE-NEXT: warning: Instruction selection used fallback path for full
12+
13+
; CHECK-GI-DOT: warning: Instruction selection used fallback path for full
814

915
define i32 @addv_v2i32(<2 x i32> %a) {
1016
; CHECK-LABEL: addv_v2i32:

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