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Revert r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
I seem to have messed up the test checks. llvm-svn: 358212
1 parent 1c2dfc3 commit 8200880

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8 files changed

+323
-382
lines changed

8 files changed

+323
-382
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 17 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -25584,18 +25584,17 @@ bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
2558425584

2558525585
// Note: this turns large loads into lock cmpxchg8b/16b.
2558625586
// TODO: In 32-bit mode, use MOVLPS when SSE1 is available?
25587+
// TODO: In 32-bit mode, use FILD/FISTP when X87 is available?
2558725588
TargetLowering::AtomicExpansionKind
2558825589
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
2558925590
Type *MemType = LI->getType();
2559025591

2559125592
// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we
25592-
// can use movq to do the load. If we have X87 we can load into an 80-bit
25593-
// X87 register and store it to a stack temporary.
25593+
// can use movq to do the load.
2559425594
bool NoImplicitFloatOps =
2559525595
LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat);
2559625596
if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
25597-
!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
25598-
(Subtarget.hasSSE2() || Subtarget.hasX87()))
25597+
!Subtarget.useSoftFloat() && !NoImplicitFloatOps && Subtarget.hasSSE2())
2559925598
return AtomicExpansionKind::None;
2560025599

2560125600
return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
@@ -27441,57 +27440,23 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
2744127440
bool NoImplicitFloatOps =
2744227441
DAG.getMachineFunction().getFunction().hasFnAttribute(
2744327442
Attribute::NoImplicitFloat);
27444-
if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps) {
27443+
if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
27444+
Subtarget.hasSSE2()) {
2744527445
auto *Node = cast<AtomicSDNode>(N);
27446-
if (Subtarget.hasSSE2()) {
27447-
// Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the
27448-
// lower 64-bits.
27449-
SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
27450-
SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
27451-
SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
27452-
MVT::i64, Node->getMemOperand());
27453-
SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
27454-
DAG.getIntPtrConstant(0, dl));
27455-
Results.push_back(Res);
27456-
Results.push_back(Ld.getValue(1));
27457-
return;
27458-
}
27459-
if (Subtarget.hasX87()) {
27460-
// First load this into an 80-bit X87 register. This will put the whole
27461-
// integer into the significand.
27462-
// FIXME: Do we need to glue? See FIXME comment in BuildFILD.
27463-
SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other, MVT::Glue);
27464-
SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
27465-
SDValue Result = DAG.getMemIntrinsicNode(X86ISD::FILD_FLAG,
27466-
dl, Tys, Ops, MVT::i64,
27467-
Node->getMemOperand());
27468-
SDValue Chain = Result.getValue(1);
27469-
SDValue InFlag = Result.getValue(2);
27470-
27471-
// Now store the X87 register to a stack temporary and convert to i64.
27472-
// This store is not atomic and doesn't need to be.
27473-
// FIXME: We don't need a stack temporary if the result of the load
27474-
// is already being stored. We could just directly store there.
27475-
SDValue StackPtr = DAG.CreateStackTemporary(MVT::i64);
27476-
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
27477-
MachinePointerInfo MPI =
27478-
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
27479-
SDValue StoreOps[] = { Chain, Result, StackPtr, InFlag };
27480-
Chain = DAG.getMemIntrinsicNode(X86ISD::FIST, dl,
27481-
DAG.getVTList(MVT::Other), StoreOps,
27482-
MVT::i64, MPI, 0 /*Align*/,
27483-
MachineMemOperand::MOStore);
27484-
27485-
// Finally load the value back from the stack temporary and return it.
27486-
// This load is not atomic and doesn't need to be.
27487-
// This load will be further type legalized.
27488-
Result = DAG.getLoad(MVT::i64, dl, Chain, StackPtr, MPI);
27489-
Results.push_back(Result);
27490-
Results.push_back(Result.getValue(1));
27491-
return;
27492-
}
27446+
// Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the lower
27447+
// 64-bits.
27448+
SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
27449+
SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
27450+
SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
27451+
MVT::i64, Node->getMemOperand());
27452+
SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
27453+
DAG.getIntPtrConstant(0, dl));
27454+
Results.push_back(Res);
27455+
Results.push_back(Ld.getValue(1));
27456+
return;
2749327457
}
2749427458
// TODO: Use MOVLPS when SSE1 is available?
27459+
// TODO: Use FILD/FISTP when X87 is available?
2749527460
// Delegate to generic TypeLegalization. Situations we can really handle
2749627461
// should have already been dealt with by AtomicExpandPass.cpp.
2749727462
break;
@@ -27684,7 +27649,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
2768427649
case X86ISD::FXOR: return "X86ISD::FXOR";
2768527650
case X86ISD::FILD: return "X86ISD::FILD";
2768627651
case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
27687-
case X86ISD::FIST: return "X86ISD::FIST";
2768827652
case X86ISD::FP_TO_INT_IN_MEM: return "X86ISD::FP_TO_INT_IN_MEM";
2768927653
case X86ISD::FLD: return "X86ISD::FLD";
2769027654
case X86ISD::FST: return "X86ISD::FST";

‎llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -608,22 +608,16 @@ namespace llvm {
608608
FILD,
609609
FILD_FLAG,
610610

611-
/// This instruction implements a fp->int store from FP stack
612-
/// slots. This corresponds to the fist instruction. It takes a
613-
/// chain operand, value to store, address, and glue. The memory VT
614-
/// specifies the type to store as.
615-
FIST,
616-
617611
/// This instruction implements an extending load to FP stack slots.
618612
/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
619613
/// operand, and ptr to load from. The memory VT specifies the type to
620614
/// load from.
621615
FLD,
622616

623-
/// This instruction implements a truncating store from FP stack
617+
/// This instruction implements a truncating store to FP stack
624618
/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
625-
/// chain operand, value to store, address, and glue. The memory VT
626-
/// specifies the type to store as.
619+
/// chain operand, value to store, and address. The memory VT specifies
620+
/// the type to store as.
627621
FST,
628622

629623
/// This instruction grabs the address of the next argument

‎llvm/lib/Target/X86/X86InstrFPStack.td

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@ def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>,
2121
def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>,
2222
SDTCisPtrTy<1>]>;
2323
def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
24-
def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
2524
def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
2625

2726
def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
@@ -36,9 +35,6 @@ def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
3635
def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
3736
[SDNPHasChain, SDNPOutGlue, SDNPMayLoad,
3837
SDNPMemOperand]>;
39-
def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist,
40-
[SDNPHasChain, SDNPInGlue, SDNPMayStore,
41-
SDNPMemOperand]>;
4238
def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>;
4339
def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst,
4440
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
@@ -83,11 +79,6 @@ def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{
8379
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
8480
}]>;
8581

86-
def X86fist64 : PatFrag<(ops node:$val, node:$ptr),
87-
(X86fist node:$val, node:$ptr), [{
88-
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
89-
}]>;
90-
9182
def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr),
9283
(X86fp_to_mem node:$val, node:$ptr), [{
9384
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
@@ -769,10 +760,6 @@ def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
769760
// Used to conv. i64 to f64 since there isn't a SSE version.
770761
def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>;
771762

772-
// Used to conv. between f80 and i64 for i64 atomic loads.
773-
def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>;
774-
def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>;
775-
776763
// FP extensions map onto simple pseudo-value conversions if they are to/from
777764
// the FP stack.
778765
def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,

‎llvm/test/CodeGen/X86/atomic-fp.ll

Lines changed: 35 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -77,13 +77,14 @@ define void @fadd_64r(double* %loc, double %val) nounwind {
7777
; X86-NOSSE-NEXT: pushl %ebx
7878
; X86-NOSSE-NEXT: pushl %esi
7979
; X86-NOSSE-NEXT: andl $-8, %esp
80-
; X86-NOSSE-NEXT: subl $24, %esp
80+
; X86-NOSSE-NEXT: subl $16, %esp
8181
; X86-NOSSE-NEXT: movl 8(%ebp), %esi
82-
; X86-NOSSE-NEXT: fildll (%esi)
83-
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
84-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
85-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
86-
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
82+
; X86-NOSSE-NEXT: xorl %eax, %eax
83+
; X86-NOSSE-NEXT: xorl %edx, %edx
84+
; X86-NOSSE-NEXT: xorl %ecx, %ecx
85+
; X86-NOSSE-NEXT: xorl %ebx, %ebx
86+
; X86-NOSSE-NEXT: lock cmpxchg8b (%esi)
87+
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
8788
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
8889
; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
8990
; X86-NOSSE-NEXT: faddl 12(%ebp)
@@ -282,12 +283,13 @@ define void @fadd_64g() nounwind {
282283
; X86-NOSSE-NEXT: movl %esp, %ebp
283284
; X86-NOSSE-NEXT: pushl %ebx
284285
; X86-NOSSE-NEXT: andl $-8, %esp
285-
; X86-NOSSE-NEXT: subl $32, %esp
286-
; X86-NOSSE-NEXT: fildll glob64
287-
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
288-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
289-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
290-
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
286+
; X86-NOSSE-NEXT: subl $24, %esp
287+
; X86-NOSSE-NEXT: xorl %eax, %eax
288+
; X86-NOSSE-NEXT: xorl %edx, %edx
289+
; X86-NOSSE-NEXT: xorl %ecx, %ecx
290+
; X86-NOSSE-NEXT: xorl %ebx, %ebx
291+
; X86-NOSSE-NEXT: lock cmpxchg8b glob64
292+
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
291293
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
292294
; X86-NOSSE-NEXT: fld1
293295
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
@@ -482,12 +484,13 @@ define void @fadd_64imm() nounwind {
482484
; X86-NOSSE-NEXT: movl %esp, %ebp
483485
; X86-NOSSE-NEXT: pushl %ebx
484486
; X86-NOSSE-NEXT: andl $-8, %esp
485-
; X86-NOSSE-NEXT: subl $32, %esp
486-
; X86-NOSSE-NEXT: fildll -559038737
487-
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
488-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
489-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
490-
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
487+
; X86-NOSSE-NEXT: subl $24, %esp
488+
; X86-NOSSE-NEXT: xorl %eax, %eax
489+
; X86-NOSSE-NEXT: xorl %edx, %edx
490+
; X86-NOSSE-NEXT: xorl %ecx, %ecx
491+
; X86-NOSSE-NEXT: xorl %ebx, %ebx
492+
; X86-NOSSE-NEXT: lock cmpxchg8b -559038737
493+
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
491494
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
492495
; X86-NOSSE-NEXT: fld1
493496
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
@@ -688,12 +691,13 @@ define void @fadd_64stack() nounwind {
688691
; X86-NOSSE-NEXT: movl %esp, %ebp
689692
; X86-NOSSE-NEXT: pushl %ebx
690693
; X86-NOSSE-NEXT: andl $-8, %esp
691-
; X86-NOSSE-NEXT: subl $40, %esp
692-
; X86-NOSSE-NEXT: fildll (%esp)
693-
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
694-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
695-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
696-
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
694+
; X86-NOSSE-NEXT: subl $32, %esp
695+
; X86-NOSSE-NEXT: xorl %eax, %eax
696+
; X86-NOSSE-NEXT: xorl %edx, %edx
697+
; X86-NOSSE-NEXT: xorl %ecx, %ecx
698+
; X86-NOSSE-NEXT: xorl %ebx, %ebx
699+
; X86-NOSSE-NEXT: lock cmpxchg8b (%esp)
700+
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
697701
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
698702
; X86-NOSSE-NEXT: fld1
699703
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
@@ -827,14 +831,15 @@ define void @fadd_array(i64* %arg, double %arg1, i64 %arg2) nounwind {
827831
; X86-NOSSE-NEXT: pushl %edi
828832
; X86-NOSSE-NEXT: pushl %esi
829833
; X86-NOSSE-NEXT: andl $-8, %esp
830-
; X86-NOSSE-NEXT: subl $32, %esp
834+
; X86-NOSSE-NEXT: subl $24, %esp
831835
; X86-NOSSE-NEXT: movl 20(%ebp), %esi
832836
; X86-NOSSE-NEXT: movl 8(%ebp), %edi
833-
; X86-NOSSE-NEXT: fildll (%edi,%esi,8)
834-
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
835-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
836-
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
837-
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
837+
; X86-NOSSE-NEXT: xorl %eax, %eax
838+
; X86-NOSSE-NEXT: xorl %edx, %edx
839+
; X86-NOSSE-NEXT: xorl %ecx, %ecx
840+
; X86-NOSSE-NEXT: xorl %ebx, %ebx
841+
; X86-NOSSE-NEXT: lock cmpxchg8b (%edi,%esi,8)
842+
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
838843
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
839844
; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
840845
; X86-NOSSE-NEXT: faddl 12(%ebp)

‎llvm/test/CodeGen/X86/atomic-load-store-wide.ll

Lines changed: 30 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -45,21 +45,22 @@ define i64 @test2(i64* %ptr) {
4545
;
4646
; NOSSE-LABEL: test2:
4747
; NOSSE: # %bb.0:
48-
; NOSSE-NEXT: pushl %ebp
48+
; NOSSE-NEXT: pushl %ebx
4949
; NOSSE-NEXT: .cfi_def_cfa_offset 8
50-
; NOSSE-NEXT: .cfi_offset %ebp, -8
51-
; NOSSE-NEXT: movl %esp, %ebp
52-
; NOSSE-NEXT: .cfi_def_cfa_register %ebp
53-
; NOSSE-NEXT: andl $-8, %esp
54-
; NOSSE-NEXT: subl $8, %esp
55-
; NOSSE-NEXT: movl 8(%ebp), %eax
56-
; NOSSE-NEXT: fildll (%eax)
57-
; NOSSE-NEXT: fistpll (%esp)
58-
; NOSSE-NEXT: movl (%esp), %eax
59-
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
60-
; NOSSE-NEXT: movl %ebp, %esp
61-
; NOSSE-NEXT: popl %ebp
62-
; NOSSE-NEXT: .cfi_def_cfa %esp, 4
50+
; NOSSE-NEXT: pushl %esi
51+
; NOSSE-NEXT: .cfi_def_cfa_offset 12
52+
; NOSSE-NEXT: .cfi_offset %esi, -12
53+
; NOSSE-NEXT: .cfi_offset %ebx, -8
54+
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
55+
; NOSSE-NEXT: xorl %eax, %eax
56+
; NOSSE-NEXT: xorl %edx, %edx
57+
; NOSSE-NEXT: xorl %ecx, %ecx
58+
; NOSSE-NEXT: xorl %ebx, %ebx
59+
; NOSSE-NEXT: lock cmpxchg8b (%esi)
60+
; NOSSE-NEXT: popl %esi
61+
; NOSSE-NEXT: .cfi_def_cfa_offset 8
62+
; NOSSE-NEXT: popl %ebx
63+
; NOSSE-NEXT: .cfi_def_cfa_offset 4
6364
; NOSSE-NEXT: retl
6465
%val = load atomic i64, i64* %ptr seq_cst, align 8
6566
ret i64 %val
@@ -101,21 +102,22 @@ define i64 @test4(i64* %ptr) {
101102
;
102103
; NOSSE-LABEL: test4:
103104
; NOSSE: # %bb.0:
104-
; NOSSE-NEXT: pushl %ebp
105+
; NOSSE-NEXT: pushl %ebx
106+
; NOSSE-NEXT: .cfi_def_cfa_offset 8
107+
; NOSSE-NEXT: pushl %esi
108+
; NOSSE-NEXT: .cfi_def_cfa_offset 12
109+
; NOSSE-NEXT: .cfi_offset %esi, -12
110+
; NOSSE-NEXT: .cfi_offset %ebx, -8
111+
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
112+
; NOSSE-NEXT: xorl %eax, %eax
113+
; NOSSE-NEXT: xorl %edx, %edx
114+
; NOSSE-NEXT: xorl %ecx, %ecx
115+
; NOSSE-NEXT: xorl %ebx, %ebx
116+
; NOSSE-NEXT: lock cmpxchg8b (%esi)
117+
; NOSSE-NEXT: popl %esi
105118
; NOSSE-NEXT: .cfi_def_cfa_offset 8
106-
; NOSSE-NEXT: .cfi_offset %ebp, -8
107-
; NOSSE-NEXT: movl %esp, %ebp
108-
; NOSSE-NEXT: .cfi_def_cfa_register %ebp
109-
; NOSSE-NEXT: andl $-8, %esp
110-
; NOSSE-NEXT: subl $8, %esp
111-
; NOSSE-NEXT: movl 8(%ebp), %eax
112-
; NOSSE-NEXT: fildll (%eax)
113-
; NOSSE-NEXT: fistpll (%esp)
114-
; NOSSE-NEXT: movl (%esp), %eax
115-
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
116-
; NOSSE-NEXT: movl %ebp, %esp
117-
; NOSSE-NEXT: popl %ebp
118-
; NOSSE-NEXT: .cfi_def_cfa %esp, 4
119+
; NOSSE-NEXT: popl %ebx
120+
; NOSSE-NEXT: .cfi_def_cfa_offset 4
119121
; NOSSE-NEXT: retl
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%val = load atomic volatile i64, i64* %ptr seq_cst, align 8
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ret i64 %val

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