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Commit 822d2cd

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author
Jun Wang
committed
Update some test files.
1 parent 0acda8c commit 822d2cd

14 files changed

+1392
-1931
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -368,12 +368,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
368368
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
369369
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)
370370
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
371-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s1)
372-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[ANYEXT]](s64)
371+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[C]](s1)
373372
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
374373
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
375-
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
376-
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
374+
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
375+
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[DEF]](p4)
377376
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
378377
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)
379378
; CHECK-NEXT: $sgpr12 = COPY [[COPY12]](s32)
@@ -426,12 +425,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
426425
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
427426
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)
428427
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
429-
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s1)
430-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[SEXT]](s64)
428+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[LOAD]](s1)
431429
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
432430
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
433-
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
434-
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
431+
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
432+
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[DEF1]](p4)
435433
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
436434
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)
437435
; CHECK-NEXT: $sgpr12 = COPY [[COPY12]](s32)
@@ -485,12 +483,11 @@ define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
485483
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
486484
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)
487485
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
488-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s1)
489-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[ZEXT]](s64)
486+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[LOAD]](s1)
490487
; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
491488
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
492-
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
493-
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
489+
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
490+
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[DEF1]](p4)
494491
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
495492
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)
496493
; CHECK-NEXT: $sgpr12 = COPY [[COPY12]](s32)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

Lines changed: 88 additions & 85 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ define i32 @load_const_i32_gv() {
2222
define i32 @load_select_const_i32_gv(i1 %cond) {
2323
; CHECK-LABEL: name: load_select_const_i32_gv
2424
; CHECK: bb.1 (%ir-block.0):
25-
; CHECK-NEXT: liveins: $sgpr0_sgpr1
25+
; CHECK-NEXT: liveins: $sgpr4_sgpr5
2626
; CHECK-NEXT: {{ $}}
27-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
27+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr4_sgpr5
2828
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
2929
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p1) = G_GLOBAL_VALUE @const_gv0
3030
; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p1) = G_GLOBAL_VALUE @const_gv1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ define float @v_div_fmas_f32(float %a, float %b, float %c, i1 %d) {
1010
; GFX7-LABEL: v_div_fmas_f32:
1111
; GFX7: ; %bb.0:
1212
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13-
; GFX7-NEXT: s_and_b32 s4, 1, s0
13+
; GFX7-NEXT: s_and_b32 s4, 1, s4
1414
; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
1515
; GFX7-NEXT: s_nop 3
1616
; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v2
@@ -19,7 +19,7 @@ define float @v_div_fmas_f32(float %a, float %b, float %c, i1 %d) {
1919
; GFX8-LABEL: v_div_fmas_f32:
2020
; GFX8: ; %bb.0:
2121
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
22-
; GFX8-NEXT: s_and_b32 s4, 1, s0
22+
; GFX8-NEXT: s_and_b32 s4, 1, s4
2323
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
2424
; GFX8-NEXT: s_nop 3
2525
; GFX8-NEXT: v_div_fmas_f32 v0, v0, v1, v2
@@ -28,15 +28,15 @@ define float @v_div_fmas_f32(float %a, float %b, float %c, i1 %d) {
2828
; GFX10_W32-LABEL: v_div_fmas_f32:
2929
; GFX10_W32: ; %bb.0:
3030
; GFX10_W32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31-
; GFX10_W32-NEXT: s_and_b32 s4, 1, s0
31+
; GFX10_W32-NEXT: s_and_b32 s4, 1, s4
3232
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
3333
; GFX10_W32-NEXT: v_div_fmas_f32 v0, v0, v1, v2
3434
; GFX10_W32-NEXT: s_setpc_b64 s[30:31]
3535
;
3636
; GFX10_W64-LABEL: v_div_fmas_f32:
3737
; GFX10_W64: ; %bb.0:
3838
; GFX10_W64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
39-
; GFX10_W64-NEXT: s_and_b32 s4, 1, s0
39+
; GFX10_W64-NEXT: s_and_b32 s4, 1, s4
4040
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
4141
; GFX10_W64-NEXT: v_div_fmas_f32 v0, v0, v1, v2
4242
; GFX10_W64-NEXT: s_setpc_b64 s[30:31]
@@ -64,7 +64,7 @@ define double @v_div_fmas_f64(double %a, double %b, double %c, i1 %d) {
6464
; GFX7-LABEL: v_div_fmas_f64:
6565
; GFX7: ; %bb.0:
6666
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
67-
; GFX7-NEXT: s_and_b32 s4, 1, s0
67+
; GFX7-NEXT: s_and_b32 s4, 1, s4
6868
; GFX7-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
6969
; GFX7-NEXT: s_nop 3
7070
; GFX7-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
@@ -73,7 +73,7 @@ define double @v_div_fmas_f64(double %a, double %b, double %c, i1 %d) {
7373
; GFX8-LABEL: v_div_fmas_f64:
7474
; GFX8: ; %bb.0:
7575
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
76-
; GFX8-NEXT: s_and_b32 s4, 1, s0
76+
; GFX8-NEXT: s_and_b32 s4, 1, s4
7777
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
7878
; GFX8-NEXT: s_nop 3
7979
; GFX8-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
@@ -82,15 +82,15 @@ define double @v_div_fmas_f64(double %a, double %b, double %c, i1 %d) {
8282
; GFX10_W32-LABEL: v_div_fmas_f64:
8383
; GFX10_W32: ; %bb.0:
8484
; GFX10_W32-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
85-
; GFX10_W32-NEXT: s_and_b32 s4, 1, s0
85+
; GFX10_W32-NEXT: s_and_b32 s4, 1, s4
8686
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
8787
; GFX10_W32-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
8888
; GFX10_W32-NEXT: s_setpc_b64 s[30:31]
8989
;
9090
; GFX10_W64-LABEL: v_div_fmas_f64:
9191
; GFX10_W64: ; %bb.0:
9292
; GFX10_W64-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
93-
; GFX10_W64-NEXT: s_and_b32 s4, 1, s0
93+
; GFX10_W64-NEXT: s_and_b32 s4, 1, s4
9494
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
9595
; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], v[0:1], v[2:3], v[4:5]
9696
; GFX10_W64-NEXT: s_setpc_b64 s[30:31]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ define void @localize_internal_globals(i1 %cond) {
168168
; GFX9-LABEL: localize_internal_globals:
169169
; GFX9: ; %bb.0: ; %entry
170170
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
171-
; GFX9-NEXT: s_and_b32 s4, 1, s0
171+
; GFX9-NEXT: s_and_b32 s4, 1, s4
172172
; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
173173
; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], -1
174174
; GFX9-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]

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