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[RISCV] Split OPERAND_SEW operand type for mask only instructions. (#119776)
Mask only instructions like vmand and vmsbf should always have 0 for their Log2SEW operand. Non-mask instructions should only have 3, 4, 5, or 6 for their Log2SEW operand. Split the operand type so we can verify these cases separately. I had to fix the SEW for whole register move to vmv.v.v copy optimization and update an mir test. The vmv.v.v change isn't functional since we have already done vsetvli insertion before and nothing else uses the field after copy expansion. I can split these changes off if desired.
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4 files changed

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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -347,8 +347,10 @@ enum OperandType : unsigned {
347347
OPERAND_COND_CODE,
348348
// Vector policy operand.
349349
OPERAND_VEC_POLICY,
350-
// Vector SEW operand.
350+
// Vector SEW operand. Stores in log2(SEW).
351351
OPERAND_SEW,
352+
// Special SEW for mask only instructions. Always 0.
353+
OPERAND_SEW_MASK,
352354
// Vector rounding mode for VXRM or FRM.
353355
OPERAND_VEC_RM,
354356
OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -430,7 +430,9 @@ void RISCVInstrInfo::copyPhysRegVector(
430430
if (UseVMV) {
431431
const MCInstrDesc &Desc = DefMBBI->getDesc();
432432
MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL
433-
MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
433+
unsigned Log2SEW =
434+
DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc)).getImm();
435+
MIB.addImm(Log2SEW ? Log2SEW : 3); // SEW
434436
MIB.addImm(0); // tu, mu
435437
MIB.addReg(RISCV::VL, RegState::Implicit);
436438
MIB.addReg(RISCV::VTYPE, RegState::Implicit);
@@ -2568,7 +2570,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25682570
Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
25692571
break;
25702572
case RISCVOp::OPERAND_SEW:
2571-
Ok = Imm == 0 || (isUInt<5>(Imm) && RISCVVType::isValidSEW(1 << Imm));
2573+
Ok = (isUInt<5>(Imm) && RISCVVType::isValidSEW(1 << Imm));
2574+
break;
2575+
case RISCVOp::OPERAND_SEW_MASK:
2576+
Ok = Imm == 0;
25722577
break;
25732578
case RISCVOp::OPERAND_VEC_RM:
25742579
assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
@@ -3206,7 +3211,8 @@ std::string RISCVInstrInfo::createMIROperandComment(
32063211
RISCVVType::printVType(Imm, OS);
32073212
break;
32083213
}
3209-
case RISCVOp::OPERAND_SEW: {
3214+
case RISCVOp::OPERAND_SEW:
3215+
case RISCVOp::OPERAND_SEW_MASK: {
32103216
unsigned Log2SEW = Op.getImm();
32113217
unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
32123218
assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 26 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,11 @@ def sew : RISCVOp {
9292
let OperandType = "OPERAND_SEW";
9393
}
9494

95+
// SEW for mask only instructions like vmand and vmsbf. Should always be 0.
96+
def sew_mask : RISCVOp {
97+
let OperandType = "OPERAND_SEW_MASK";
98+
}
99+
95100
def vec_rm : RISCVOp {
96101
let OperandType = "OPERAND_VEC_RM";
97102
}
@@ -781,9 +786,10 @@ class GetVTypePredicates<VTypeInfo vti> {
781786
}
782787

783788
class VPseudoUSLoadNoMask<VReg RetClass,
784-
int EEW> :
789+
int EEW,
790+
DAGOperand sewop = sew> :
785791
Pseudo<(outs RetClass:$rd),
786-
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew,
792+
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
787793
vec_policy:$policy), []>,
788794
RISCVVPseudo,
789795
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -929,9 +935,10 @@ class VPseudoILoadMask<VReg RetClass,
929935
}
930936

931937
class VPseudoUSStoreNoMask<VReg StClass,
932-
int EEW> :
938+
int EEW,
939+
DAGOperand sewop = sew> :
933940
Pseudo<(outs),
934-
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
941+
(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
935942
RISCVVPseudo,
936943
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
937944
let mayLoad = 0;
@@ -1015,7 +1022,7 @@ class VPseudoNullaryMask<VReg RegClass> :
10151022
// Nullary for pseudo instructions. They are expanded in
10161023
// RISCVExpandPseudoInsts pass.
10171024
class VPseudoNullaryPseudoM<string BaseInst> :
1018-
Pseudo<(outs VR:$rd), (ins AVL:$vl, sew:$sew), []>,
1025+
Pseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew), []>,
10191026
RISCVVPseudo {
10201027
let mayLoad = 0;
10211028
let mayStore = 0;
@@ -1052,7 +1059,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
10521059
string Constraint = "",
10531060
bits<2> TargetConstraintType = 1> :
10541061
Pseudo<(outs RetClass:$rd),
1055-
(ins OpClass:$rs2, AVL:$vl, sew:$sew), []>,
1062+
(ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []>,
10561063
RISCVVPseudo {
10571064
let mayLoad = 0;
10581065
let mayStore = 0;
@@ -1087,10 +1094,11 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
10871094
class VPseudoUnaryMask<VReg RetClass,
10881095
VReg OpClass,
10891096
string Constraint = "",
1090-
bits<2> TargetConstraintType = 1> :
1097+
bits<2> TargetConstraintType = 1,
1098+
DAGOperand sewop = sew> :
10911099
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
10921100
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1093-
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1101+
VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []>,
10941102
RISCVVPseudo {
10951103
let mayLoad = 0;
10961104
let mayStore = 0;
@@ -1145,7 +1153,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
11451153

11461154
class VPseudoUnaryNoMaskGPROut :
11471155
Pseudo<(outs GPR:$rd),
1148-
(ins VR:$rs2, AVL:$vl, sew:$sew), []>,
1156+
(ins VR:$rs2, AVL:$vl, sew_mask:$sew), []>,
11491157
RISCVVPseudo {
11501158
let mayLoad = 0;
11511159
let mayStore = 0;
@@ -1156,7 +1164,7 @@ class VPseudoUnaryNoMaskGPROut :
11561164

11571165
class VPseudoUnaryMaskGPROut :
11581166
Pseudo<(outs GPR:$rd),
1159-
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
1167+
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []>,
11601168
RISCVVPseudo {
11611169
let mayLoad = 0;
11621170
let mayStore = 0;
@@ -1184,9 +1192,10 @@ class VPseudoBinaryNoMask<VReg RetClass,
11841192
VReg Op1Class,
11851193
DAGOperand Op2Class,
11861194
string Constraint,
1187-
bits<2> TargetConstraintType = 1> :
1195+
bits<2> TargetConstraintType = 1,
1196+
DAGOperand sewop = sew> :
11881197
Pseudo<(outs RetClass:$rd),
1189-
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew), []>,
1198+
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []>,
11901199
RISCVVPseudo {
11911200
let mayLoad = 0;
11921201
let mayStore = 0;
@@ -1859,7 +1868,7 @@ multiclass VPseudoLoadMask {
18591868
defvar mx = mti.LMul.MX;
18601869
defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
18611870
let VLMul = mti.LMul.value in {
1862-
def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1>,
1871+
def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1, sewop=sew_mask>,
18631872
Sched<[WriteVLDM_MX, ReadVLDX]>;
18641873
}
18651874
}
@@ -1934,7 +1943,7 @@ multiclass VPseudoStoreMask {
19341943
defvar mx = mti.LMul.MX;
19351944
defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
19361945
let VLMul = mti.LMul.value in {
1937-
def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1>,
1946+
def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1, sewop=sew_mask>,
19381947
Sched<[WriteVSTM_MX, ReadVSTX]>;
19391948
}
19401949
}
@@ -2018,7 +2027,8 @@ multiclass VPseudoVSFS_M {
20182027
SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
20192028
forcePassthruRead=true>;
20202029
let ForceTailAgnostic = true in
2021-
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
2030+
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint,
2031+
sewop = sew_mask>,
20222032
SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
20232033
forcePassthruRead=true>;
20242034
}
@@ -2275,7 +2285,7 @@ multiclass VPseudoBinaryV_VI_RM<Operand ImmType, LMULInfo m, string Constraint =
22752285
multiclass VPseudoVALU_MM<bit Commutable = 0> {
22762286
foreach mti = AllMasks in {
22772287
let VLMul = mti.LMul.value, isCommutable = Commutable in {
2278-
def "_MM_" # mti.BX : VPseudoBinaryNoMask<VR, VR, VR, "">,
2288+
def "_MM_" # mti.BX : VPseudoBinaryNoMask<VR, VR, VR, "", sewop = sew_mask>,
22792289
SchedBinary<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", mti.LMul.MX>;
22802290
}
22812291
}

‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@ body: |
1313
; CHECK-NEXT: %false:vr = COPY $v8
1414
; CHECK-NEXT: %true:vr = COPY $v9
1515
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
16-
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
16+
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */
1717
; CHECK-NEXT: $v0 = COPY %mask
1818
%false:vr = COPY $v8
1919
%true:vr = COPY $v9
2020
%avl:gprnox0 = COPY $x1
21-
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 5
21+
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 0
2222
$v0 = COPY %mask
2323
%x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, $v0, %avl, 5
2424
...
@@ -34,14 +34,14 @@ body: |
3434
; CHECK-NEXT: %false:vr = COPY $noreg
3535
; CHECK-NEXT: %true:vr = COPY $v9
3636
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
37-
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
37+
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */
3838
; CHECK-NEXT: $v0 = COPY %mask
3939
; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl, 5 /* e32 */, 0 /* tu, mu */
4040
%pt:vrnov0 = COPY $v8
4141
%false:vr = COPY $noreg
4242
%true:vr = COPY $v9
4343
%avl:gprnox0 = COPY $x1
44-
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 5
44+
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 0
4545
$v0 = COPY %mask
4646
%x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, $v0, %avl, 5
4747
...
@@ -57,14 +57,14 @@ body: |
5757
; CHECK-NEXT: %pt:vr = COPY $v8
5858
; CHECK-NEXT: %true:vr = COPY $v9
5959
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
60-
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
60+
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */
6161
; CHECK-NEXT: $v0 = COPY %mask
6262
; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl, 5 /* e32 */, 0 /* tu, mu */
6363
%false:vr = COPY $v8
6464
%pt:vrnov0 = COPY $v8
6565
%true:vr = COPY $v9
6666
%avl:gprnox0 = COPY $x1
67-
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 5
67+
%mask:vmv0 = PseudoVMSET_M_B8 %avl, 0
6868
$v0 = COPY %mask
6969
%x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, $v0, %avl, 5
7070
...

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