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[PowerPC] Add code to spill and restore DMRp registers (#142443)
1 parent d9f7979 commit 82acd8c

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6 files changed

+300
-71
lines changed

6 files changed

+300
-71
lines changed

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1926,7 +1926,7 @@ unsigned PPCInstrInfo::getSpillIndex(const TargetRegisterClass *RC) const {
19261926
} else if (PPC::DMRROWpRCRegClass.hasSubClassEq(RC)) {
19271927
llvm_unreachable("TODO: Implement spill DMRROWp regclass!");
19281928
} else if (PPC::DMRpRCRegClass.hasSubClassEq(RC)) {
1929-
llvm_unreachable("TODO: Implement spill DMRp regclass!");
1929+
OpcodeIndex = SOK_DMRpSpill;
19301930
} else if (PPC::DMRRCRegClass.hasSubClassEq(RC)) {
19311931
OpcodeIndex = SOK_DMRSpill;
19321932
} else {

‎llvm/lib/Target/PowerPC/PPCInstrInfo.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ enum SpillOpcodeKey {
8181
SOK_AccumulatorSpill,
8282
SOK_UAccumulatorSpill,
8383
SOK_WAccumulatorSpill,
84+
SOK_DMRpSpill,
8485
SOK_DMRSpill,
8586
SOK_SPESpill,
8687
SOK_PairedG8Spill,
@@ -119,6 +120,7 @@ enum PPCMachineCombinerPattern : unsigned {
119120
NoInstr, \
120121
NoInstr, \
121122
NoInstr, \
123+
NoInstr, \
122124
PPC::EVLDD, \
123125
PPC::RESTORE_QUADWORD}
124126

@@ -140,6 +142,7 @@ enum PPCMachineCombinerPattern : unsigned {
140142
NoInstr, \
141143
NoInstr, \
142144
NoInstr, \
145+
NoInstr, \
143146
PPC::RESTORE_QUADWORD}
144147

145148
#define Pwr10LoadOpcodes \
@@ -160,6 +163,7 @@ enum PPCMachineCombinerPattern : unsigned {
160163
NoInstr, \
161164
NoInstr, \
162165
NoInstr, \
166+
NoInstr, \
163167
PPC::RESTORE_QUADWORD}
164168

165169
#define FutureLoadOpcodes \
@@ -178,6 +182,7 @@ enum PPCMachineCombinerPattern : unsigned {
178182
PPC::RESTORE_ACC, \
179183
PPC::RESTORE_UACC, \
180184
PPC::RESTORE_WACC, \
185+
PPC::RESTORE_DMRP, \
181186
PPC::RESTORE_DMR, \
182187
NoInstr, \
183188
PPC::RESTORE_QUADWORD}
@@ -199,6 +204,7 @@ enum PPCMachineCombinerPattern : unsigned {
199204
NoInstr, \
200205
NoInstr, \
201206
NoInstr, \
207+
NoInstr, \
202208
PPC::EVSTDD, \
203209
PPC::SPILL_QUADWORD}
204210

@@ -220,6 +226,7 @@ enum PPCMachineCombinerPattern : unsigned {
220226
NoInstr, \
221227
NoInstr, \
222228
NoInstr, \
229+
NoInstr, \
223230
PPC::SPILL_QUADWORD}
224231

225232
#define Pwr10StoreOpcodes \
@@ -240,6 +247,7 @@ enum PPCMachineCombinerPattern : unsigned {
240247
NoInstr, \
241248
NoInstr, \
242249
NoInstr, \
250+
NoInstr, \
243251
PPC::SPILL_QUADWORD}
244252

245253
#define FutureStoreOpcodes \
@@ -258,6 +266,7 @@ enum PPCMachineCombinerPattern : unsigned {
258266
PPC::SPILL_ACC, \
259267
PPC::SPILL_UACC, \
260268
PPC::SPILL_WACC, \
269+
PPC::SPILL_DMRP, \
261270
PPC::SPILL_DMR, \
262271
NoInstr, \
263272
PPC::SPILL_QUADWORD}

‎llvm/lib/Target/PowerPC/PPCInstrMMA.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -565,12 +565,16 @@ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
565565
let mayStore = 1 in {
566566
def SPILL_WACC: PPCEmitTimePseudo<(outs), (ins wacc:$AT, memrix16:$dst),
567567
"#SPILL_WACC", []>;
568+
def SPILL_DMRP: PPCEmitTimePseudo<(outs), (ins dmrp:$AT, memrix16:$dst),
569+
"#SPILL_DMRP", []>;
568570
def SPILL_DMR: PPCEmitTimePseudo<(outs), (ins dmr:$AT, memrix16:$dst),
569571
"#SPILL_DMR", []>;
570572
}
571573
let mayLoad = 1, hasSideEffects = 0 in {
572574
def RESTORE_WACC: PPCEmitTimePseudo<(outs wacc:$AT), (ins memrix16:$src),
573575
"#RESTORE_WACC", []>;
576+
def RESTORE_DMRP: PPCEmitTimePseudo<(outs dmrp:$AT), (ins memrix16:$src),
577+
"#RESTORE_DMRP", []>;
574578
def RESTORE_DMR: PPCEmitTimePseudo<(outs dmr:$AT), (ins memrix16:$src),
575579
"#RESTORE_DMR", []>;
576580
}

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 55 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1519,33 +1519,32 @@ void PPCRegisterInfo::lowerDMRSpilling(MachineBasicBlock::iterator II,
15191519
// DMR is made up of WACC and WACC_HI, so DMXXEXTFDMR512 to spill
15201520
// the corresponding 512 bits.
15211521
const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1522-
Register SrcReg = MI.getOperand(0).getReg();
1523-
1524-
Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1525-
Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1526-
Register VSRpReg2 = MF.getRegInfo().createVirtualRegister(RC);
1527-
Register VSRpReg3 = MF.getRegInfo().createVirtualRegister(RC);
1522+
auto spillDMR = [&](Register SrcReg, int BEIdx, int LEIdx) {
1523+
auto spillWACC = [&](unsigned Opc, unsigned RegIdx, int IdxBE, int IdxLE) {
1524+
Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1525+
Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1526+
1527+
BuildMI(MBB, II, DL, TII.get(Opc), VSRpReg0)
1528+
.addDef(VSRpReg1)
1529+
.addReg(TargetRegisterInfo::getSubReg(SrcReg, RegIdx));
1530+
1531+
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1532+
.addReg(VSRpReg0, RegState::Kill),
1533+
FrameIndex, IsLittleEndian ? IdxLE : IdxBE);
1534+
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1535+
.addReg(VSRpReg1, RegState::Kill),
1536+
FrameIndex, IsLittleEndian ? IdxLE - 32 : IdxBE + 32);
1537+
};
1538+
spillWACC(PPC::DMXXEXTFDMR512, PPC::sub_wacc_lo, BEIdx, LEIdx);
1539+
spillWACC(PPC::DMXXEXTFDMR512_HI, PPC::sub_wacc_hi, BEIdx + 64, LEIdx - 64);
1540+
};
15281541

1529-
BuildMI(MBB, II, DL, TII.get(PPC::DMXXEXTFDMR512_HI), VSRpReg2)
1530-
.addDef(VSRpReg3)
1531-
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_wacc_hi));
1532-
1533-
BuildMI(MBB, II, DL, TII.get(PPC::DMXXEXTFDMR512), VSRpReg0)
1534-
.addDef(VSRpReg1)
1535-
.addReg(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_wacc_lo));
1536-
1537-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1538-
.addReg(VSRpReg0, RegState::Kill),
1539-
FrameIndex, IsLittleEndian ? 96 : 0);
1540-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1541-
.addReg(VSRpReg1, RegState::Kill),
1542-
FrameIndex, IsLittleEndian ? 64 : 32);
1543-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1544-
.addReg(VSRpReg2, RegState::Kill),
1545-
FrameIndex, IsLittleEndian ? 32 : 64);
1546-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1547-
.addReg(VSRpReg3, RegState::Kill),
1548-
FrameIndex, IsLittleEndian ? 0 : 96);
1542+
Register SrcReg = MI.getOperand(0).getReg();
1543+
if (MI.getOpcode() == PPC::SPILL_DMRP) {
1544+
spillDMR(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_dmr1), 0, 96);
1545+
spillDMR(TargetRegisterInfo::getSubReg(SrcReg, PPC::sub_dmr0), 128, 224);
1546+
} else
1547+
spillDMR(SrcReg, 0, 96);
15491548

15501549
// Discard the pseudo instruction.
15511550
MBB.erase(II);
@@ -1554,7 +1553,7 @@ void PPCRegisterInfo::lowerDMRSpilling(MachineBasicBlock::iterator II,
15541553
/// lowerDMRRestore - Generate the code to restore the DMR register.
15551554
void PPCRegisterInfo::lowerDMRRestore(MachineBasicBlock::iterator II,
15561555
unsigned FrameIndex) const {
1557-
MachineInstr &MI = *II; // <DestReg> = RESTORE_WACC <offset>
1556+
MachineInstr &MI = *II; // <DestReg> = RESTORE_DMR[P] <offset>
15581557
MachineBasicBlock &MBB = *MI.getParent();
15591558
MachineFunction &MF = *MBB.getParent();
15601559
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
@@ -1563,32 +1562,34 @@ void PPCRegisterInfo::lowerDMRRestore(MachineBasicBlock::iterator II,
15631562
bool IsLittleEndian = Subtarget.isLittleEndian();
15641563

15651564
const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1566-
Register DestReg = MI.getOperand(0).getReg();
1567-
1568-
Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1569-
Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1570-
Register VSRpReg2 = MF.getRegInfo().createVirtualRegister(RC);
1571-
Register VSRpReg3 = MF.getRegInfo().createVirtualRegister(RC);
1565+
auto restoreDMR = [&](Register DestReg, int BEIdx, int LEIdx) {
1566+
auto restoreWACC = [&](unsigned Opc, unsigned RegIdx, int IdxBE,
1567+
int IdxLE) {
1568+
Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1569+
Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1570+
1571+
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg0),
1572+
FrameIndex, IsLittleEndian ? IdxLE : IdxBE);
1573+
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg1),
1574+
FrameIndex, IsLittleEndian ? IdxLE - 32 : IdxBE + 32);
1575+
1576+
// Kill virtual registers (killedRegState::Killed).
1577+
BuildMI(MBB, II, DL, TII.get(Opc),
1578+
TargetRegisterInfo::getSubReg(DestReg, RegIdx))
1579+
.addReg(VSRpReg0, RegState::Kill)
1580+
.addReg(VSRpReg1, RegState::Kill);
1581+
};
1582+
restoreWACC(PPC::DMXXINSTDMR512, PPC::sub_wacc_lo, BEIdx, LEIdx);
1583+
restoreWACC(PPC::DMXXINSTDMR512_HI, PPC::sub_wacc_hi, BEIdx + 64,
1584+
LEIdx - 64);
1585+
};
15721586

1573-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg0),
1574-
FrameIndex, IsLittleEndian ? 96 : 0);
1575-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg1),
1576-
FrameIndex, IsLittleEndian ? 64 : 32);
1577-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg2),
1578-
FrameIndex, IsLittleEndian ? 32 : 64);
1579-
addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg3),
1580-
FrameIndex, IsLittleEndian ? 0 : 96);
1581-
1582-
// Kill virtual registers (killedRegState::Killed).
1583-
BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512_HI),
1584-
TargetRegisterInfo::getSubReg(DestReg, PPC::sub_wacc_hi))
1585-
.addReg(VSRpReg2, RegState::Kill)
1586-
.addReg(VSRpReg3, RegState::Kill);
1587-
1588-
BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512),
1589-
TargetRegisterInfo::getSubReg(DestReg, PPC::sub_wacc_lo))
1590-
.addReg(VSRpReg0, RegState::Kill)
1591-
.addReg(VSRpReg1, RegState::Kill);
1587+
Register DestReg = MI.getOperand(0).getReg();
1588+
if (MI.getOpcode() == PPC::RESTORE_DMRP) {
1589+
restoreDMR(TargetRegisterInfo::getSubReg(DestReg, PPC::sub_dmr1), 0, 96);
1590+
restoreDMR(TargetRegisterInfo::getSubReg(DestReg, PPC::sub_dmr0), 128, 224);
1591+
} else
1592+
restoreDMR(DestReg, 0, 96);
15921593

15931594
// Discard the pseudo instruction.
15941595
MBB.erase(II);
@@ -1756,9 +1757,11 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
17561757
case PPC::RESTORE_WACC:
17571758
lowerWACCRestore(II, FrameIndex);
17581759
return true;
1760+
case PPC::SPILL_DMRP:
17591761
case PPC::SPILL_DMR:
17601762
lowerDMRSpilling(II, FrameIndex);
17611763
return true;
1764+
case PPC::RESTORE_DMRP:
17621765
case PPC::RESTORE_DMR:
17631766
lowerDMRRestore(II, FrameIndex);
17641767
return true;

‎llvm/test/CodeGen/PowerPC/dmr-spill.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -30,19 +30,19 @@ define void @spillDMRreg(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) nounwind {
3030
; CHECK-NEXT: lxv v3, 0(r4)
3131
; CHECK-NEXT: lxv vs0, 0(r5)
3232
; CHECK-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0
33+
; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
34+
; CHECK-NEXT: stxvp vsp36, 128(r1)
35+
; CHECK-NEXT: stxvp vsp34, 96(r1)
3336
; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc_hi0, 1
34-
; CHECK-NEXT: dmxxextfdmr512 vsp38, vsp32, wacc0, 0
35-
; CHECK-NEXT: stxvp vsp38, 128(r1)
36-
; CHECK-NEXT: stxvp vsp32, 96(r1)
3737
; CHECK-NEXT: stxvp vsp36, 64(r1)
3838
; CHECK-NEXT: stxvp vsp34, 32(r1)
3939
; CHECK-NEXT: bl dummy_func@notoc
4040
; CHECK-NEXT: lxvp vsp34, 128(r1)
4141
; CHECK-NEXT: lxvp vsp36, 96(r1)
42-
; CHECK-NEXT: lxvp vsp32, 64(r1)
43-
; CHECK-NEXT: lxvp vsp38, 32(r1)
44-
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp32, vsp38, 1
4542
; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
43+
; CHECK-NEXT: lxvp vsp34, 64(r1)
44+
; CHECK-NEXT: lxvp vsp36, 32(r1)
45+
; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
4646
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
4747
; CHECK-NEXT: stxvp vsp34, 96(r30)
4848
; CHECK-NEXT: stxvp vsp36, 64(r30)
@@ -72,20 +72,20 @@ define void @spillDMRreg(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) nounwind {
7272
; AIX-NEXT: lxv v3, 16(r4)
7373
; AIX-NEXT: lxv vs0, 0(r5)
7474
; AIX-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0
75+
; AIX-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
76+
; AIX-NEXT: stxvp vsp36, 112(r1)
77+
; AIX-NEXT: stxvp vsp34, 144(r1)
7578
; AIX-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc_hi0, 1
76-
; AIX-NEXT: dmxxextfdmr512 vsp38, vsp32, wacc0, 0
77-
; AIX-NEXT: stxvp vsp38, 112(r1)
78-
; AIX-NEXT: stxvp vsp32, 144(r1)
7979
; AIX-NEXT: stxvp vsp36, 176(r1)
8080
; AIX-NEXT: stxvp vsp34, 208(r1)
8181
; AIX-NEXT: bl .dummy_func[PR]
8282
; AIX-NEXT: nop
8383
; AIX-NEXT: lxvp vsp34, 112(r1)
8484
; AIX-NEXT: lxvp vsp36, 144(r1)
85-
; AIX-NEXT: lxvp vsp32, 176(r1)
86-
; AIX-NEXT: lxvp vsp38, 208(r1)
87-
; AIX-NEXT: dmxxinstdmr512 wacc_hi0, vsp32, vsp38, 1
8885
; AIX-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
86+
; AIX-NEXT: lxvp vsp34, 176(r1)
87+
; AIX-NEXT: lxvp vsp36, 208(r1)
88+
; AIX-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
8989
; AIX-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
9090
; AIX-NEXT: stxvp vsp36, 96(r31)
9191
; AIX-NEXT: stxvp vsp34, 64(r31)
@@ -115,20 +115,20 @@ define void @spillDMRreg(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) nounwind {
115115
; AIX32-NEXT: lxv v3, 16(r4)
116116
; AIX32-NEXT: lxv vs0, 0(r5)
117117
; AIX32-NEXT: dmxvbf16gerx2pp dmr0, vsp34, vs0
118+
; AIX32-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
119+
; AIX32-NEXT: stxvp vsp36, 64(r1)
120+
; AIX32-NEXT: stxvp vsp34, 96(r1)
118121
; AIX32-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc_hi0, 1
119-
; AIX32-NEXT: dmxxextfdmr512 vsp38, vsp32, wacc0, 0
120-
; AIX32-NEXT: stxvp vsp38, 64(r1)
121-
; AIX32-NEXT: stxvp vsp32, 96(r1)
122122
; AIX32-NEXT: stxvp vsp36, 128(r1)
123123
; AIX32-NEXT: stxvp vsp34, 160(r1)
124124
; AIX32-NEXT: bl .dummy_func[PR]
125125
; AIX32-NEXT: nop
126126
; AIX32-NEXT: lxvp vsp34, 64(r1)
127127
; AIX32-NEXT: lxvp vsp36, 96(r1)
128-
; AIX32-NEXT: lxvp vsp32, 128(r1)
129-
; AIX32-NEXT: lxvp vsp38, 160(r1)
130-
; AIX32-NEXT: dmxxinstdmr512 wacc_hi0, vsp32, vsp38, 1
131128
; AIX32-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
129+
; AIX32-NEXT: lxvp vsp34, 128(r1)
130+
; AIX32-NEXT: lxvp vsp36, 160(r1)
131+
; AIX32-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1
132132
; AIX32-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
133133
; AIX32-NEXT: stxvp vsp36, 96(r31)
134134
; AIX32-NEXT: stxvp vsp34, 64(r31)

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