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MDevereauMDevereau
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[AArch64][SME2] Refine fcvtu/fcvts/scvtf/ucvtf
Rename intrinsics for fcvtu to fcvtzu and fcvts to fcvtzs. Use llvm_anyvector_ty for both multi vector returns and operands, therefore the return and operands can be specified in the intrinsic call, e.g. @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32
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‎clang/include/clang/Basic/TargetBuiltins.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,7 @@ namespace clang {
310310
bool isReadZA() const { return Flags & IsReadZA; }
311311
bool isWriteZA() const { return Flags & IsWriteZA; }
312312
bool isReductionQV() const { return Flags & IsReductionQV; }
313+
bool isOverloadMultiVecCvt() const { return Flags & IsOverloadMultiVecCvt; }
313314
uint64_t getBits() const { return Flags; }
314315
bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
315316
};

‎clang/include/clang/Basic/arm_sve.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2244,15 +2244,15 @@ let TargetGuard = "sme2" in {
22442244
def SVCVT_F16_X2 : SInst<"svcvt_f16[_f32_x2]", "e2", "f", MergeNone, "aarch64_sve_fcvt_x2", [IsStreaming],[]>;
22452245
def SVCVT_BF16_X2 : SInst<"svcvt_bf16[_f32_x2]", "$2", "f", MergeNone, "aarch64_sve_bfcvt_x2", [IsOverloadNone, IsStreaming],[]>;
22462246

2247-
def SVCVT_F32_U32_X2 : SInst<"svcvt_{d}[_u32_x2]", "2.d2.u", "f", MergeNone, "aarch64_sve_ucvtf_x2", [IsStreaming], []>;
2248-
def SVCVT_U32_F32_X2 : SInst<"svcvt_u32[_{d}_x2]", "2.u2.d", "f", MergeNone, "aarch64_sve_fcvtu_x2", [IsStreaming], []>;
2249-
def SVCVT_F32_S32_X2 : SInst<"svcvt_{d}[_s32_x2]", "2.d2.x", "f", MergeNone, "aarch64_sve_scvtf_x2", [IsStreaming], []>;
2250-
def SVCVT_S32_F32_X2 : SInst<"svcvt_s32[_{d}_x2]", "2.x2.d", "f", MergeNone, "aarch64_sve_fcvts_x2", [IsStreaming], []>;
2251-
2252-
def SVCVT_F32_U32_X4 : SInst<"svcvt_{d}[_u32_x4]", "4.d4.u", "f", MergeNone, "aarch64_sve_ucvtf_x4", [IsStreaming], []>;
2253-
def SVCVT_U32_F32_X4 : SInst<"svcvt_u32[_{d}_x4]", "4.u4.d", "f", MergeNone, "aarch64_sve_fcvtu_x4", [IsStreaming], []>;
2254-
def SVCVT_F32_S32_X4 : SInst<"svcvt_{d}[_s32_x4]", "4.d4.x", "f", MergeNone, "aarch64_sve_scvtf_x4", [IsStreaming], []>;
2255-
def SVCVT_S32_F32_X4 : SInst<"svcvt_s32[_{d}_x4]", "4.x4.d", "f", MergeNone, "aarch64_sve_fcvts_x4", [IsStreaming], []>;
2247+
def SVCVT_F32_U32_X2 : SInst<"svcvt_{d}[_u32_x2]", "2.d2.u", "f", MergeNone, "aarch64_sve_ucvtf_x2", [IsStreaming, IsOverloadMultiVecCvt], []>;
2248+
def SVCVT_U32_F32_X2 : SInst<"svcvt_{d}[_f32_x2]", "2.d2.M", "Ui", MergeNone, "aarch64_sve_fcvtzu_x2", [IsStreaming, IsOverloadMultiVecCvt], []>;
2249+
def SVCVT_F32_S32_X2 : SInst<"svcvt_{d}[_s32_x2]", "2.d2.x", "f", MergeNone, "aarch64_sve_scvtf_x2", [IsStreaming, IsOverloadMultiVecCvt], []>;
2250+
def SVCVT_S32_F32_X2 : SInst<"svcvt_{d}[_f32_x2]", "2.d2.M", "i", MergeNone, "aarch64_sve_fcvtzs_x2", [IsStreaming, IsOverloadMultiVecCvt], []>;
2251+
2252+
def SVCVT_F32_U32_X4 : SInst<"svcvt_{d}[_u32_x4]", "4.d4.u", "f", MergeNone, "aarch64_sve_ucvtf_x4", [IsStreaming, IsOverloadMultiVecCvt], []>;
2253+
def SVCVT_U32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "Ui", MergeNone, "aarch64_sve_fcvtzu_x4", [IsStreaming, IsOverloadMultiVecCvt], []>;
2254+
def SVCVT_F32_S32_X4 : SInst<"svcvt_{d}[_s32_x4]", "4.d4.x", "f", MergeNone, "aarch64_sve_scvtf_x4", [IsStreaming, IsOverloadMultiVecCvt], []>;
2255+
def SVCVT_S32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "i", MergeNone, "aarch64_sve_fcvtzs_x4", [IsStreaming, IsOverloadMultiVecCvt], []>;
22562256
}
22572257

22582258
//

‎clang/include/clang/Basic/arm_sve_sme_incl.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,7 @@ def IsStreamingOrSVE2p1 : FlagType<0x40000000000>; // Use for intrinsics t
229229
def IsInZA : FlagType<0x80000000000>;
230230
def IsOutZA : FlagType<0x100000000000>;
231231
def IsInOutZA : FlagType<0x200000000000>;
232+
def IsOverloadMultiVecCvt : FlagType<0x400000000000>;
232233

233234
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
234235
class ImmCheckType<int val> {

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10056,7 +10056,7 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags &TypeFlags,
1005610056

1005710057
llvm::Type *DefaultType = getSVEType(TypeFlags);
1005810058

10059-
if (TypeFlags.isOverloadWhile())
10059+
if (TypeFlags.isOverloadWhile() || TypeFlags.isOverloadMultiVecCvt())
1006010060
return {DefaultType, Ops[1]->getType()};
1006110061

1006210062
if (TypeFlags.isOverloadWhileRW())

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c

Lines changed: 16 additions & 16 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -3095,26 +3095,14 @@ let TargetPrefix = "aarch64" in {
30953095
[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
30963096
[IntrNoMem]>;
30973097

3098-
class SME2_CVT_ItoF_X2_Intrinsic
3098+
class SME2_CVT_X2_Intrinsic
30993099
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
3100-
[LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>],
3100+
[llvm_anyvector_ty, LLVMMatchType<1>],
31013101
[IntrNoMem]>;
31023102

3103-
class SME2_CVT_FtoI_X2_Intrinsic
3104-
: DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>],
3105-
[llvm_anyvector_ty, LLVMMatchType<0>],
3106-
[IntrNoMem]>;
3107-
3108-
class SME2_CVT_ItoF_X4_Intrinsic
3103+
class SME2_CVT_X4_Intrinsic
31093104
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
3110-
[LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>,
3111-
LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>],
3112-
[IntrNoMem]>;
3113-
3114-
class SME2_CVT_FtoI_X4_Intrinsic
3115-
: DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>,
3116-
LLVMVectorOfBitcastsToInt<0>, LLVMVectorOfBitcastsToInt<0>],
3117-
[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
3105+
[llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>],
31183106
[IntrNoMem]>;
31193107

31203108
class SME2_BFMLS_Intrinsic
@@ -3403,14 +3391,14 @@ let TargetPrefix = "aarch64" in {
34033391
//
34043392
def int_aarch64_sve_fcvt_x2 : SME2_CVT_VG2_SINGLE_Intrinsic;
34053393
def int_aarch64_sve_bfcvt_x2 : SME2_CVT_VG2_SINGLE_BF16_Intrinsic;
3406-
def int_aarch64_sve_fcvts_x2 : SME2_CVT_FtoI_X2_Intrinsic;
3407-
def int_aarch64_sve_fcvtu_x2 : SME2_CVT_FtoI_X2_Intrinsic;
3408-
def int_aarch64_sve_scvtf_x2 : SME2_CVT_ItoF_X2_Intrinsic;
3409-
def int_aarch64_sve_ucvtf_x2 : SME2_CVT_ItoF_X2_Intrinsic;
3410-
def int_aarch64_sve_fcvts_x4 : SME2_CVT_FtoI_X4_Intrinsic;
3411-
def int_aarch64_sve_fcvtu_x4 : SME2_CVT_FtoI_X4_Intrinsic;
3412-
def int_aarch64_sve_scvtf_x4 : SME2_CVT_ItoF_X4_Intrinsic;
3413-
def int_aarch64_sve_ucvtf_x4 : SME2_CVT_ItoF_X4_Intrinsic;
3394+
def int_aarch64_sve_fcvtzs_x2 : SME2_CVT_X2_Intrinsic;
3395+
def int_aarch64_sve_fcvtzu_x2 : SME2_CVT_X2_Intrinsic;
3396+
def int_aarch64_sve_scvtf_x2 : SME2_CVT_X2_Intrinsic;
3397+
def int_aarch64_sve_ucvtf_x2 : SME2_CVT_X2_Intrinsic;
3398+
def int_aarch64_sve_fcvtzs_x4 : SME2_CVT_X4_Intrinsic;
3399+
def int_aarch64_sve_fcvtzu_x4 : SME2_CVT_X4_Intrinsic;
3400+
def int_aarch64_sve_scvtf_x4 : SME2_CVT_X4_Intrinsic;
3401+
def int_aarch64_sve_ucvtf_x4 : SME2_CVT_X4_Intrinsic;
34143402

34153403
//
34163404
// Multi-vector saturating extract narrow

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5627,25 +5627,25 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
56275627
AArch64::FMINNM_VG4_4Z4Z_D}))
56285628
SelectDestructiveMultiIntrinsic(Node, 4, true, Op);
56295629
return;
5630-
case Intrinsic::aarch64_sve_fcvts_x2:
5630+
case Intrinsic::aarch64_sve_fcvtzs_x2:
56315631
SelectCVTIntrinsic(Node, 2, AArch64::FCVTZS_2Z2Z_StoS);
56325632
return;
56335633
case Intrinsic::aarch64_sve_scvtf_x2:
56345634
SelectCVTIntrinsic(Node, 2, AArch64::SCVTF_2Z2Z_StoS);
56355635
return;
5636-
case Intrinsic::aarch64_sve_fcvtu_x2:
5636+
case Intrinsic::aarch64_sve_fcvtzu_x2:
56375637
SelectCVTIntrinsic(Node, 2, AArch64::FCVTZU_2Z2Z_StoS);
56385638
return;
56395639
case Intrinsic::aarch64_sve_ucvtf_x2:
56405640
SelectCVTIntrinsic(Node, 2, AArch64::UCVTF_2Z2Z_StoS);
56415641
return;
5642-
case Intrinsic::aarch64_sve_fcvts_x4:
5642+
case Intrinsic::aarch64_sve_fcvtzs_x4:
56435643
SelectCVTIntrinsic(Node, 4, AArch64::FCVTZS_4Z4Z_StoS);
56445644
return;
56455645
case Intrinsic::aarch64_sve_scvtf_x4:
56465646
SelectCVTIntrinsic(Node, 4, AArch64::SCVTF_4Z4Z_StoS);
56475647
return;
5648-
case Intrinsic::aarch64_sve_fcvtu_x4:
5648+
case Intrinsic::aarch64_sve_fcvtzu_x4:
56495649
SelectCVTIntrinsic(Node, 4, AArch64::FCVTZU_4Z4Z_StoS);
56505650
return;
56515651
case Intrinsic::aarch64_sve_ucvtf_x4:

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-cvt.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @multi_vector_cvt_x2_s32_f32(<v
4141
; CHECK-NEXT: mov z2.d, z1.d
4242
; CHECK-NEXT: fcvtzs { z0.s, z1.s }, { z2.s, z3.s }
4343
; CHECK-NEXT: ret
44-
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvts.x2.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)
44+
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)
4545
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
4646
}
4747

@@ -54,7 +54,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x
5454
; CHECK-NEXT: mov z4.d, z1.d
5555
; CHECK-NEXT: fcvtzs { z0.s - z3.s }, { z4.s - z7.s }
5656
; CHECK-NEXT: ret
57-
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvts.x4.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)
57+
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x4.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)
5858
ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %res
5959
}
6060

@@ -68,7 +68,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @multi_vector_cvt_x2_u32_f32(<v
6868
; CHECK-NEXT: mov z2.d, z1.d
6969
; CHECK-NEXT: fcvtzu { z0.s, z1.s }, { z2.s, z3.s }
7070
; CHECK-NEXT: ret
71-
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtu.x2.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)
71+
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)
7272
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
7373
}
7474

@@ -81,7 +81,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
8181
; CHECK-NEXT: mov z4.d, z1.d
8282
; CHECK-NEXT: fcvtzu { z0.s - z3.s }, { z4.s - z7.s }
8383
; CHECK-NEXT: ret
84-
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtu.x4.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)
84+
%res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x4.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)
8585
ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %res
8686
}
8787

@@ -95,7 +95,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_x2_f32_s3
9595
; CHECK-NEXT: mov z2.d, z1.d
9696
; CHECK-NEXT: scvtf { z0.s, z1.s }, { z2.s, z3.s }
9797
; CHECK-NEXT: ret
98-
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x2.nxv4f32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)
98+
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)
9999
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
100100
}
101101

@@ -108,7 +108,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale
108108
; CHECK-NEXT: mov z4.d, z1.d
109109
; CHECK-NEXT: scvtf { z0.s - z3.s }, { z4.s - z7.s }
110110
; CHECK-NEXT: ret
111-
%res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x4.nxv4f32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)
111+
%res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)
112112
ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res
113113
}
114114

@@ -122,7 +122,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_x2_f32_u3
122122
; CHECK-NEXT: mov z2.d, z1.d
123123
; CHECK-NEXT: ucvtf { z0.s, z1.s }, { z2.s, z3.s }
124124
; CHECK-NEXT: ret
125-
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x2.nxv4f32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)
125+
%res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)
126126
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
127127
}
128128

@@ -135,17 +135,17 @@ define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale
135135
; CHECK-NEXT: mov z4.d, z1.d
136136
; CHECK-NEXT: ucvtf { z0.s - z3.s }, { z4.s - z7.s }
137137
; CHECK-NEXT: ret
138-
%res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x4.nxv4f32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)
138+
%res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)
139139
ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res
140140
}
141141

142142
declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
143143
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>)
144-
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvts.x2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)
145-
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtu.x2.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)
146-
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x2.nxv4f32(<vscale x 4 x i32>,<vscale x 4 x i32>)
147-
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x2.nxv4f32(<vscale x 4 x i32>,<vscale x 4 x i32>)
148-
declare {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvts.x4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>)
149-
declare {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtu.x4.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>)
150-
declare {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x4.nxv4f32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
151-
declare {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x4.nxv4f32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
144+
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)
145+
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)
146+
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>)
147+
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>)
148+
declare {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x4.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>)
149+
declare {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x4.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>)
150+
declare {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
151+
declare {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)

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