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Leon Clark
committed
Address review comments.
1 parent 795fb8c commit 83a5243

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-56
lines changed

3 files changed

+55
-56
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‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -446,9 +446,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
446446
{ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
447447
MVT::i64, Custom);
448448

449-
for (auto VT : {MVT::i8, MVT::i16}) {
449+
for (auto VT : {MVT::i8, MVT::i16})
450450
setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom);
451-
}
452451

453452
static const MVT::SimpleValueType VectorIntTypes[] = {
454453
MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32,
@@ -3085,10 +3084,10 @@ SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
30853084
assert(ResultVT == Arg.getValueType());
30863085

30873086
auto const LeadingZeroes = 32u - ResultVT.getFixedSizeInBits();
3088-
auto SubVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32);
30893087
auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg);
3088+
auto ShiftVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32);
3089+
NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, ShiftVal);
30903090
NewOp = DAG.getNode(Op.getOpcode(), SL, MVT::i32, NewOp);
3091-
NewOp = DAG.getNode(ISD::SUB, SL, MVT::i32, NewOp, SubVal);
30923091
return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp);
30933092
}
30943093

‎llvm/test/CodeGen/AMDGPU/ctlz.ll

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -492,9 +492,9 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
492492
; SI-NEXT: s_mov_b32 s4, s0
493493
; SI-NEXT: s_mov_b32 s5, s1
494494
; SI-NEXT: s_waitcnt vmcnt(0)
495+
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
495496
; SI-NEXT: v_ffbh_u32_e32 v0, v0
496497
; SI-NEXT: v_min_u32_e32 v0, 32, v0
497-
; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0
498498
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
499499
; SI-NEXT: s_endpgm
500500
;
@@ -512,17 +512,17 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
512512
; VI-NEXT: s_mov_b32 s4, s0
513513
; VI-NEXT: s_mov_b32 s5, s1
514514
; VI-NEXT: s_waitcnt vmcnt(0)
515+
; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
515516
; VI-NEXT: v_ffbh_u32_e32 v0, v0
516517
; VI-NEXT: v_min_u32_e32 v0, 32, v0
517-
; VI-NEXT: v_subrev_u32_e32 v0, vcc, 24, v0
518518
; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
519519
; VI-NEXT: s_endpgm
520520
;
521521
; EG-LABEL: v_ctlz_i8:
522522
; EG: ; %bb.0:
523523
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
524524
; EG-NEXT: TEX 0 @6
525-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
525+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
526526
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
527527
; EG-NEXT: CF_END
528528
; EG-NEXT: PAD
@@ -531,14 +531,15 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
531531
; EG-NEXT: ALU clause starting at 8:
532532
; EG-NEXT: MOV * T0.X, KC0[2].Z,
533533
; EG-NEXT: ALU clause starting at 9:
534-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
535-
; EG-NEXT: CNDE_INT T0.W, T0.X, literal.x, PV.W,
536-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
537-
; EG-NEXT: 32(4.484155e-44), 3(4.203895e-45)
538-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
539-
; EG-NEXT: -24(nan), 0(0.000000e+00)
534+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
535+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
536+
; EG-NEXT: FFBH_UINT T1.W, PV.W,
537+
; EG-NEXT: AND_INT * T2.W, KC0[2].Y, literal.x,
538+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
539+
; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W,
540+
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
540541
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
541-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
542+
; EG-NEXT: LSHL * T1.W, T2.W, literal.y,
542543
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
543544
; EG-NEXT: LSHL T0.X, PV.W, PS,
544545
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -555,9 +556,9 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
555556
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
556557
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3]
557558
; GFX10-NEXT: s_waitcnt vmcnt(0)
559+
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 24, v1
558560
; GFX10-NEXT: v_ffbh_u32_e32 v1, v1
559561
; GFX10-NEXT: v_min_u32_e32 v1, 32, v1
560-
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 24, v1
561562
; GFX10-NEXT: global_store_byte v0, v1, s[0:1]
562563
; GFX10-NEXT: s_endpgm
563564
;
@@ -581,10 +582,10 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
581582
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
582583
; GFX11-NEXT: global_load_u8 v1, v0, s[2:3]
583584
; GFX11-NEXT: s_waitcnt vmcnt(0)
584-
; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1
585+
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
585586
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
587+
; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1
586588
; GFX11-NEXT: v_min_u32_e32 v1, 32, v1
587-
; GFX11-NEXT: v_subrev_nc_u32_e32 v1, 24, v1
588589
; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]
589590
; GFX11-NEXT: s_nop 0
590591
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)

‎llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll

Lines changed: 38 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -314,9 +314,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
314314
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
315315
; SI-NEXT: s_mov_b32 s3, 0xf000
316316
; SI-NEXT: s_waitcnt lgkmcnt(0)
317-
; SI-NEXT: s_and_b32 s2, s2, 0xff
318-
; SI-NEXT: s_flbit_i32_b32 s2, s2
319-
; SI-NEXT: s_sub_i32 s4, s2, 24
317+
; SI-NEXT: s_lshl_b32 s2, s2, 24
318+
; SI-NEXT: s_flbit_i32_b32 s4, s2
320319
; SI-NEXT: s_mov_b32 s2, -1
321320
; SI-NEXT: v_mov_b32_e32 v0, s4
322321
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -327,9 +326,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
327326
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
328327
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
329328
; VI-NEXT: s_waitcnt lgkmcnt(0)
330-
; VI-NEXT: s_and_b32 s2, s2, 0xff
329+
; VI-NEXT: s_lshl_b32 s2, s2, 24
331330
; VI-NEXT: s_flbit_i32_b32 s2, s2
332-
; VI-NEXT: s_sub_i32 s2, s2, 24
333331
; VI-NEXT: v_mov_b32_e32 v0, s0
334332
; VI-NEXT: v_mov_b32_e32 v1, s1
335333
; VI-NEXT: v_mov_b32_e32 v2, s2
@@ -349,13 +347,13 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
349347
; EG-NEXT: ALU clause starting at 8:
350348
; EG-NEXT: MOV * T0.X, 0.0,
351349
; EG-NEXT: ALU clause starting at 9:
352-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
350+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
351+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
352+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
353353
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
354354
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
355-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
356-
; EG-NEXT: -24(nan), 0(0.000000e+00)
357355
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
358-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
356+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
359357
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
360358
; EG-NEXT: LSHL T0.X, PV.W, PS,
361359
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -391,9 +389,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
391389
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
392390
; SI-NEXT: s_mov_b32 s3, 0xf000
393391
; SI-NEXT: s_waitcnt lgkmcnt(0)
394-
; SI-NEXT: s_and_b32 s2, s2, 0xffff
395-
; SI-NEXT: s_flbit_i32_b32 s2, s2
396-
; SI-NEXT: s_add_i32 s4, s2, -16
392+
; SI-NEXT: s_lshl_b32 s2, s2, 16
393+
; SI-NEXT: s_flbit_i32_b32 s4, s2
397394
; SI-NEXT: s_mov_b32 s2, -1
398395
; SI-NEXT: v_mov_b32_e32 v0, s4
399396
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
@@ -426,13 +423,13 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
426423
; EG-NEXT: ALU clause starting at 8:
427424
; EG-NEXT: MOV * T0.X, 0.0,
428425
; EG-NEXT: ALU clause starting at 9:
429-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
426+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
427+
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
428+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
430429
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
431430
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
432-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
433-
; EG-NEXT: -16(nan), 0(0.000000e+00)
434431
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
435-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
432+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
436433
; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
437434
; EG-NEXT: LSHL T0.X, PV.W, PS,
438435
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -590,8 +587,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
590587
; SI-NEXT: s_mov_b32 s4, s0
591588
; SI-NEXT: s_mov_b32 s5, s1
592589
; SI-NEXT: s_waitcnt vmcnt(0)
593-
; SI-NEXT: v_ffbh_u32_e32 v1, v0
594-
; SI-NEXT: v_subrev_i32_e32 v1, vcc, 24, v1
590+
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
591+
; SI-NEXT: v_ffbh_u32_e32 v1, v1
595592
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
596593
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc
597594
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
@@ -605,8 +602,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
605602
; VI-NEXT: v_mov_b32_e32 v1, s3
606603
; VI-NEXT: flat_load_ubyte v0, v[0:1]
607604
; VI-NEXT: s_waitcnt vmcnt(0)
608-
; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
609-
; VI-NEXT: v_subrev_u32_e32 v1, vcc, 24, v1
605+
; VI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
606+
; VI-NEXT: v_ffbh_u32_e32 v1, v1
610607
; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
611608
; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc
612609
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -618,7 +615,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
618615
; EG: ; %bb.0:
619616
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
620617
; EG-NEXT: TEX 0 @6
621-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
618+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
622619
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
623620
; EG-NEXT: CF_END
624621
; EG-NEXT: PAD
@@ -627,10 +624,11 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
627624
; EG-NEXT: ALU clause starting at 8:
628625
; EG-NEXT: MOV * T0.X, KC0[2].Z,
629626
; EG-NEXT: ALU clause starting at 9:
630-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
631-
; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,
632-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
633-
; EG-NEXT: -24(nan), 3(4.203895e-45)
627+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
628+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
629+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
630+
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
631+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
634632
; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,
635633
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
636634
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
@@ -685,8 +683,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
685683
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
686684
; SI-NEXT: s_waitcnt vmcnt(0)
687685
; SI-NEXT: v_or_b32_e32 v0, v0, v1
688-
; SI-NEXT: v_ffbh_u32_e32 v1, v0
689-
; SI-NEXT: v_add_i32_e32 v1, vcc, -16, v1
686+
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
687+
; SI-NEXT: v_ffbh_u32_e32 v1, v1
690688
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
691689
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc
692690
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
@@ -721,7 +719,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
721719
; EG: ; %bb.0:
722720
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
723721
; EG-NEXT: TEX 0 @6
724-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
722+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
725723
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
726724
; EG-NEXT: CF_END
727725
; EG-NEXT: PAD
@@ -730,10 +728,11 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
730728
; EG-NEXT: ALU clause starting at 8:
731729
; EG-NEXT: MOV * T0.X, KC0[2].Z,
732730
; EG-NEXT: ALU clause starting at 9:
733-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
734-
; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,
735-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
736-
; EG-NEXT: -16(nan), 3(4.203895e-45)
731+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
732+
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
733+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
734+
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
735+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
737736
; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,
738737
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
739738
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
@@ -1102,8 +1101,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11021101
; SI-NEXT: s_mov_b32 s4, s0
11031102
; SI-NEXT: s_mov_b32 s5, s1
11041103
; SI-NEXT: s_waitcnt vmcnt(0)
1104+
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
11051105
; SI-NEXT: v_ffbh_u32_e32 v0, v0
1106-
; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0
11071106
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
11081107
; SI-NEXT: s_endpgm
11091108
;
@@ -1116,8 +1115,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11161115
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
11171116
; VI-NEXT: flat_load_ubyte v0, v[0:1]
11181117
; VI-NEXT: s_waitcnt vmcnt(0)
1119-
; VI-NEXT: v_ffbh_u32_e32 v0, v0
1120-
; VI-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
1118+
; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
1119+
; VI-NEXT: v_ffbh_u32_e32 v2, v0
11211120
; VI-NEXT: v_mov_b32_e32 v0, s0
11221121
; VI-NEXT: v_mov_b32_e32 v1, s1
11231122
; VI-NEXT: flat_store_byte v[0:1], v2
@@ -1136,13 +1135,13 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11361135
; EG-NEXT: ALU clause starting at 8:
11371136
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,
11381137
; EG-NEXT: ALU clause starting at 9:
1139-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
1138+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
1139+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
1140+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
11401141
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
11411142
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
1142-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
1143-
; EG-NEXT: -24(nan), 0(0.000000e+00)
11441143
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
1145-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
1144+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
11461145
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
11471146
; EG-NEXT: LSHL T0.X, PV.W, PS,
11481147
; EG-NEXT: LSHL * T0.W, literal.x, PS,

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