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[GlobalISel] Handle div-by-pow2
This patch adds similar handling of div-by-pow2 as in `SelectionDAG`.
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+2487
-730
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7 files changed

+2487
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‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -673,6 +673,14 @@ class CombinerHelper {
673673
bool matchSDivByConst(MachineInstr &MI);
674674
void applySDivByConst(MachineInstr &MI);
675675

676+
/// Given an G_SDIV \p MI expressing a signed divided by a pow2 constant,
677+
/// return expressions that implements it by shifting.
678+
bool matchDivByPow2(MachineInstr &MI, bool IsSigned);
679+
void applySDivByPow2(MachineInstr &MI);
680+
/// Given an G_UDIV \p MI expressing an unsigned divided by a pow2 constant,
681+
/// return expressions that implements it by shifting.
682+
void applyUDivByPow2(MachineInstr &MI);
683+
676684
// G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
677685
bool matchUMulHToLShr(MachineInstr &MI);
678686
void applyUMulHToLShr(MachineInstr &MI);

‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,7 @@ def FmArcp : MIFlagEnum<"FmArcp">;
179179
def FmContract : MIFlagEnum<"FmContract">;
180180
def FmAfn : MIFlagEnum<"FmAfn">;
181181
def FmReassoc : MIFlagEnum<"FmReassoc">;
182+
def IsExact : MIFlagEnum<"IsExact">;
182183

183184
def MIFlags;
184185
// def not; -> Already defined as a SDNode
@@ -1036,7 +1037,20 @@ def sdiv_by_const : GICombineRule<
10361037
[{ return Helper.matchSDivByConst(*${root}); }]),
10371038
(apply [{ Helper.applySDivByConst(*${root}); }])>;
10381039

1039-
def intdiv_combines : GICombineGroup<[udiv_by_const, sdiv_by_const]>;
1040+
def sdiv_by_pow2 : GICombineRule<
1041+
(defs root:$root),
1042+
(match (G_SDIV $dst, $x, $y, (MIFlags (not IsExact))):$root,
1043+
[{ return Helper.matchDivByPow2(*${root}, /*IsSigned=*/true); }]),
1044+
(apply [{ Helper.applySDivByPow2(*${root}); }])>;
1045+
1046+
def udiv_by_pow2 : GICombineRule<
1047+
(defs root:$root),
1048+
(match (G_UDIV $dst, $x, $y, (MIFlags (not IsExact))):$root,
1049+
[{ return Helper.matchDivByPow2(*${root}, /*IsSigned=*/false); }]),
1050+
(apply [{ Helper.applyUDivByPow2(*${root}); }])>;
1051+
1052+
def intdiv_combines : GICombineGroup<[udiv_by_const, sdiv_by_const,
1053+
sdiv_by_pow2, udiv_by_pow2]>;
10401054

10411055
def reassoc_ptradd : GICombineRule<
10421056
(defs root:$root, build_fn_matchinfo:$matchinfo),

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5268,6 +5268,146 @@ MachineInstr *CombinerHelper::buildSDivUsingMul(MachineInstr &MI) {
52685268
return MIB.buildMul(Ty, Res, Factor);
52695269
}
52705270

5271+
bool CombinerHelper::matchDivByPow2(MachineInstr &MI, bool IsSigned) {
5272+
assert((MI.getOpcode() == TargetOpcode::G_SDIV ||
5273+
MI.getOpcode() == TargetOpcode::G_UDIV) &&
5274+
"Expected SDIV or UDIV");
5275+
auto &Div = cast<GenericMachineInstr>(MI);
5276+
Register RHS = Div.getReg(2);
5277+
auto MatchPow2 = [&](const Constant *C) {
5278+
auto *CI = dyn_cast<ConstantInt>(C);
5279+
return CI && (CI->getValue().isPowerOf2() ||
5280+
(IsSigned && CI->getValue().isNegatedPowerOf2()));
5281+
};
5282+
return matchUnaryPredicate(MRI, RHS, MatchPow2, /*AllowUndefs=*/false);
5283+
}
5284+
5285+
void CombinerHelper::applySDivByPow2(MachineInstr &MI) {
5286+
assert(MI.getOpcode() == TargetOpcode::G_SDIV && "Expected SDIV");
5287+
auto &SDiv = cast<GenericMachineInstr>(MI);
5288+
Register Dst = SDiv.getReg(0);
5289+
Register LHS = SDiv.getReg(1);
5290+
Register RHS = SDiv.getReg(2);
5291+
LLT Ty = MRI.getType(Dst);
5292+
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
5293+
5294+
Builder.setInstrAndDebugLoc(MI);
5295+
5296+
// Effectively we want to lower G_SDIV %lhs, %rhs, where %rhs is a power of 2,
5297+
// to the following version:
5298+
//
5299+
// %c1 = G_CTTZ %rhs
5300+
// %inexact = G_SUB $bitwidth, %c1
5301+
// %sign = %G_ASHR %lhs, $(bitwidth - 1)
5302+
// %srl = G_SHL %sign, %inexact
5303+
// %add = G_ADD %lhs, %srl
5304+
// %sra = G_ASHR %add, %c1
5305+
// %sra = G_SELECT, %isoneorallones, %lhs, %sra
5306+
// %zero = G_CONSTANT $0
5307+
// %neg = G_NEG %sra
5308+
// %isneg = G_ICMP SLT %lhs, %zero
5309+
// %res = G_SELECT %isneg, %neg, %sra
5310+
//
5311+
// When %rhs is a constant integer, or a splat vector, we can check its value
5312+
// at compile time such that the first two G_ICMP conditional statements, as
5313+
// well as the corresponding non-taken branches, can be eliminated. This can
5314+
// generate compact code even w/o any constant folding afterwards. When $rhs
5315+
// is not a splat vector, we have to generate those checks via instructions.
5316+
5317+
unsigned Bitwidth = Ty.getScalarSizeInBits();
5318+
auto Zero = Builder.buildConstant(Ty, 0);
5319+
5320+
// TODO: It is not necessary to have this specialized version. We need it *for
5321+
// now* because the folding/combine can't handle it. Remove this large
5322+
// conditional statement once we can properly fold the two G_ICMP.
5323+
if (auto RHSC = getConstantOrConstantSplatVector(RHS)) {
5324+
// Special case: (sdiv X, 1) -> X
5325+
if (RHSC->isOne()) {
5326+
replaceSingleDefInstWithReg(MI, LHS);
5327+
return;
5328+
}
5329+
// Special Case: (sdiv X, -1) -> 0-X
5330+
if (RHSC->isAllOnes()) {
5331+
auto Neg = Builder.buildNeg(Ty, LHS);
5332+
replaceSingleDefInstWithReg(MI, Neg->getOperand(0).getReg());
5333+
return;
5334+
}
5335+
5336+
unsigned TrailingZeros = RHSC->countTrailingZeros();
5337+
auto C1 = Builder.buildConstant(ShiftAmtTy, TrailingZeros);
5338+
auto Inexact = Builder.buildConstant(ShiftAmtTy, Bitwidth - TrailingZeros);
5339+
auto Sign = Builder.buildAShr(
5340+
Ty, LHS, Builder.buildConstant(ShiftAmtTy, Bitwidth - 1));
5341+
// Add (LHS < 0) ? abs2 - 1 : 0;
5342+
auto Shl = Builder.buildShl(Ty, Sign, Inexact);
5343+
auto Add = Builder.buildAdd(Ty, LHS, Shl);
5344+
auto Shr = Builder.buildAShr(Ty, Add, C1);
5345+
5346+
// If dividing by a positive value, we're done. Otherwise, the result must
5347+
// be negated.
5348+
auto Res = RHSC->isNegative() ? Builder.buildNeg(Ty, Shr) : Shr;
5349+
replaceSingleDefInstWithReg(MI, Res->getOperand(0).getReg());
5350+
return;
5351+
}
5352+
5353+
// RHS is not a splat vector. Build the above version with instructions.
5354+
auto Bits = Builder.buildConstant(ShiftAmtTy, Bitwidth);
5355+
auto C1 = Builder.buildCTTZ(Ty, RHS);
5356+
C1 = Builder.buildZExtOrTrunc(ShiftAmtTy, C1);
5357+
auto Inexact = Builder.buildSub(ShiftAmtTy, Bits, C1);
5358+
auto Sign = Builder.buildAShr(
5359+
Ty, LHS, Builder.buildConstant(ShiftAmtTy, Bitwidth - 1));
5360+
5361+
// Add (LHS < 0) ? abs2 - 1 : 0;
5362+
auto Shl = Builder.buildShl(Ty, Sign, Inexact);
5363+
auto Add = Builder.buildAdd(Ty, LHS, Shl);
5364+
auto Shr = Builder.buildAShr(Ty, Add, C1);
5365+
5366+
LLT CCVT = LLT::vector(Ty.getElementCount(), 1);
5367+
5368+
auto One = Builder.buildConstant(Ty, 1);
5369+
auto AllOnes =
5370+
Builder.buildConstant(Ty, APInt::getAllOnes(Ty.getScalarSizeInBits()));
5371+
auto IsOne = Builder.buildICmp(CmpInst::Predicate::ICMP_EQ, CCVT, RHS, One);
5372+
auto IsAllOnes =
5373+
Builder.buildICmp(CmpInst::Predicate::ICMP_EQ, CCVT, RHS, AllOnes);
5374+
auto IsOneOrAllOnes = Builder.buildOr(CCVT, IsOne, IsAllOnes);
5375+
Shr = Builder.buildSelect(Ty, IsOneOrAllOnes, LHS, Shr);
5376+
5377+
// If dividing by a positive value, we're done. Otherwise, the result must
5378+
// be negated.
5379+
auto Neg = Builder.buildNeg(Ty, Shr);
5380+
auto IsNeg = Builder.buildICmp(CmpInst::Predicate::ICMP_SLT, CCVT, LHS, Zero);
5381+
auto Res = Builder.buildSelect(Ty, IsNeg, Neg, Shr);
5382+
replaceSingleDefInstWithReg(MI, Res->getOperand(0).getReg());
5383+
}
5384+
5385+
void CombinerHelper::applyUDivByPow2(MachineInstr &MI) {
5386+
assert(MI.getOpcode() == TargetOpcode::G_UDIV && "Expected UDIV");
5387+
auto &UDiv = cast<GenericMachineInstr>(MI);
5388+
Register Dst = UDiv.getReg(0);
5389+
Register LHS = UDiv.getReg(1);
5390+
Register RHS = UDiv.getReg(2);
5391+
LLT Ty = MRI.getType(Dst);
5392+
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
5393+
5394+
Builder.setInstrAndDebugLoc(MI);
5395+
5396+
// TODO: It is not necessary to have this specialized version. We need it *for
5397+
// now* because the folding/combine can't handle CTTZ.
5398+
if (auto RHSC = getConstantOrConstantSplatVector(RHS)) {
5399+
auto C1 = Builder.buildConstant(ShiftAmtTy, RHSC->countTrailingZeros());
5400+
auto Res = Builder.buildLShr(Ty, LHS, C1);
5401+
replaceSingleDefInstWithReg(MI, Res->getOperand(0).getReg());
5402+
return;
5403+
}
5404+
5405+
auto C1 = Builder.buildCTTZ(Ty, RHS);
5406+
C1 = Builder.buildZExtOrTrunc(ShiftAmtTy, C1);
5407+
auto Res = Builder.buildLShr(Ty, LHS, C1);
5408+
replaceSingleDefInstWithReg(MI, Res->getOperand(0).getReg());
5409+
}
5410+
52715411
bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) {
52725412
assert(MI.getOpcode() == TargetOpcode::G_UMULH);
52735413
Register RHS = MI.getOperand(2).getReg();

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sbfe.ll

Lines changed: 12 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -670,36 +670,19 @@ define amdgpu_kernel void @bfe_sext_in_reg_i24(ptr addrspace(1) %out, ptr addrsp
670670
define amdgpu_kernel void @simplify_demanded_bfe_sdiv(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
671671
; GFX6-LABEL: simplify_demanded_bfe_sdiv:
672672
; GFX6: ; %bb.0:
673-
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, 2.0
674-
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
675-
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
676-
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
673+
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0
677674
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
678-
; GFX6-NEXT: s_load_dword s0, s[6:7], 0x0
679-
; GFX6-NEXT: s_mov_b32 s6, -1
680-
; GFX6-NEXT: s_mov_b32 s7, 0xf000
681-
; GFX6-NEXT: v_mul_lo_u32 v1, v0, -2
682-
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
683-
; GFX6-NEXT: s_bfe_i32 s0, s0, 0x100001
684-
; GFX6-NEXT: s_ashr_i32 s2, s0, 31
685-
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
686-
; GFX6-NEXT: s_add_i32 s0, s0, s2
687-
; GFX6-NEXT: s_xor_b32 s0, s0, s2
688-
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
689-
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
690-
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v0
691-
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
692-
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
693-
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 2, v1
694-
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
695-
; GFX6-NEXT: v_subrev_i32_e64 v2, s[0:1], 2, v1
696-
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
697-
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
698-
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 2, v1
699-
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
700-
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0
701-
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
702-
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
675+
; GFX6-NEXT: s_load_dword s3, s[2:3], 0x0
676+
; GFX6-NEXT: s_mov_b32 s2, -1
677+
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
678+
; GFX6-NEXT: s_bfe_i32 s3, s3, 0x100001
679+
; GFX6-NEXT: s_ashr_i32 s4, s3, 31
680+
; GFX6-NEXT: s_lshl_b32 s4, s4, 31
681+
; GFX6-NEXT: s_add_i32 s3, s3, s4
682+
; GFX6-NEXT: s_ashr_i32 s3, s3, 1
683+
; GFX6-NEXT: v_mov_b32_e32 v0, s3
684+
; GFX6-NEXT: s_mov_b32 s3, 0xf000
685+
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
703686
; GFX6-NEXT: s_endpgm
704687
%src = load i32, ptr addrspace(1) %in, align 4
705688
%bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src, i32 1, i32 16)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll

Lines changed: 14 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -279,125 +279,27 @@ define i32 @v_sdiv_i32_pow2k_denom(i32 %num) {
279279
; CHECK: ; %bb.0:
280280
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
281281
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0
282-
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, 0x45800000
283-
; CHECK-NEXT: v_mov_b32_e32 v3, 0xfffff000
284-
; CHECK-NEXT: v_mov_b32_e32 v4, 0x1000
282+
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 20, v1
285283
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1
286-
; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
287-
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
288-
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
289-
; CHECK-NEXT: v_mul_lo_u32 v3, v2, v3
290-
; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
291-
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
292-
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2
293-
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 12, v2
294-
; CHECK-NEXT: v_add_i32_e32 v5, vcc, 1, v2
295-
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
296-
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
297-
; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
298-
; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, 0x1000, v0
299-
; CHECK-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
300-
; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2
301-
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
302-
; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
303-
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1
304-
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
284+
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0
305285
; CHECK-NEXT: s_setpc_b64 s[30:31]
306286
%result = sdiv i32 %num, 4096
307287
ret i32 %result
308288
}
309289

310290
define <2 x i32> @v_sdiv_v2i32_pow2k_denom(<2 x i32> %num) {
311-
; GISEL-LABEL: v_sdiv_v2i32_pow2k_denom:
312-
; GISEL: ; %bb.0:
313-
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
314-
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0
315-
; GISEL-NEXT: v_mov_b32_e32 v3, 0x1000
316-
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x1000
317-
; GISEL-NEXT: v_mov_b32_e32 v5, 0xfffff000
318-
; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1
319-
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2
320-
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
321-
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6
322-
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
323-
; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
324-
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
325-
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
326-
; GISEL-NEXT: v_mul_lo_u32 v5, v4, v5
327-
; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5
328-
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
329-
; GISEL-NEXT: v_mul_hi_u32 v5, v0, v4
330-
; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4
331-
; GISEL-NEXT: v_lshlrev_b32_e32 v7, 12, v5
332-
; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v5
333-
; GISEL-NEXT: v_lshlrev_b32_e32 v9, 12, v4
334-
; GISEL-NEXT: v_add_i32_e32 v10, vcc, 1, v4
335-
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
336-
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
337-
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
338-
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[4:5]
339-
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v0, v3
340-
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v1, v3
341-
; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[6:7]
342-
; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, 0x1000, v1
343-
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v7, s[4:5]
344-
; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5
345-
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
346-
; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4
347-
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
348-
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc
349-
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
350-
; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc
351-
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
352-
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6
353-
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
354-
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
355-
; GISEL-NEXT: s_setpc_b64 s[30:31]
356-
;
357-
; CGP-LABEL: v_sdiv_v2i32_pow2k_denom:
358-
; CGP: ; %bb.0:
359-
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
360-
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v0
361-
; CGP-NEXT: v_rcp_iflag_f32_e32 v3, 0x45800000
362-
; CGP-NEXT: v_mov_b32_e32 v4, 0xfffff000
363-
; CGP-NEXT: v_mov_b32_e32 v5, 0x1000
364-
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1
365-
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
366-
; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
367-
; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6
368-
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
369-
; CGP-NEXT: v_cvt_u32_f32_e32 v3, v3
370-
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
371-
; CGP-NEXT: v_mul_lo_u32 v4, v3, v4
372-
; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
373-
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4
374-
; CGP-NEXT: v_mul_hi_u32 v4, v0, v3
375-
; CGP-NEXT: v_mul_hi_u32 v3, v1, v3
376-
; CGP-NEXT: v_lshlrev_b32_e32 v7, 12, v4
377-
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
378-
; CGP-NEXT: v_lshlrev_b32_e32 v9, 12, v3
379-
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v3
380-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
381-
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
382-
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v5
383-
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[4:5]
384-
; CGP-NEXT: v_sub_i32_e32 v7, vcc, v0, v5
385-
; CGP-NEXT: v_cmp_ge_u32_e64 s[6:7], v1, v5
386-
; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[6:7]
387-
; CGP-NEXT: v_subrev_i32_e32 v8, vcc, 0x1000, v1
388-
; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v7, s[4:5]
389-
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4
390-
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
391-
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v3
392-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
393-
; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
394-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
395-
; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
396-
; CGP-NEXT: v_xor_b32_e32 v0, v0, v2
397-
; CGP-NEXT: v_xor_b32_e32 v1, v1, v6
398-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
399-
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
400-
; CGP-NEXT: s_setpc_b64 s[30:31]
291+
; CHECK-LABEL: v_sdiv_v2i32_pow2k_denom:
292+
; CHECK: ; %bb.0:
293+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
294+
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v0
295+
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
296+
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 20, v2
297+
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 20, v3
298+
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
299+
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3
300+
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0
301+
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 12, v1
302+
; CHECK-NEXT: s_setpc_b64 s[30:31]
401303
%result = sdiv <2 x i32> %num, <i32 4096, i32 4096>
402304
ret <2 x i32> %result
403305
}

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