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Add SVE run line
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‎llvm/test/CodeGen/AArch64/alias_mask_scalable.ll

Lines changed: 146 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1,81 +1,194 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=aarch64 -mattr=+sve2 %s -o - | FileCheck %s
2+
; RUN: llc -mtriple=aarch64 -mattr=+sve2 %s -o - | FileCheck %s --check-prefix=CHECK-SVE2
3+
; RUN: llc -mtriple=aarch64 -mattr=+sve %s -o - | FileCheck %s --check-prefix=CHECK-SVE
34

45
define <vscale x 16 x i1> @whilewr_8(i64 %a, i64 %b) {
5-
; CHECK-LABEL: whilewr_8:
6-
; CHECK: // %bb.0: // %entry
7-
; CHECK-NEXT: whilewr p0.b, x0, x1
8-
; CHECK-NEXT: ret
6+
; CHECK-SVE2-LABEL: whilewr_8:
7+
; CHECK-SVE2: // %bb.0: // %entry
8+
; CHECK-SVE2-NEXT: whilewr p0.b, x0, x1
9+
; CHECK-SVE2-NEXT: ret
10+
;
11+
; CHECK-SVE-LABEL: whilewr_8:
12+
; CHECK-SVE: // %bb.0: // %entry
13+
; CHECK-SVE-NEXT: sub x8, x1, x0
14+
; CHECK-SVE-NEXT: cmp x8, #1
15+
; CHECK-SVE-NEXT: cset w9, lt
16+
; CHECK-SVE-NEXT: whilelo p0.b, #0, x8
17+
; CHECK-SVE-NEXT: sbfx x8, x9, #0, #1
18+
; CHECK-SVE-NEXT: whilelo p1.b, xzr, x8
19+
; CHECK-SVE-NEXT: sel p0.b, p0, p0.b, p1.b
20+
; CHECK-SVE-NEXT: ret
921
entry:
1022
%0 = call <vscale x 16 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 1, i1 1)
1123
ret <vscale x 16 x i1> %0
1224
}
1325

1426
define <vscale x 8 x i1> @whilewr_16(i64 %a, i64 %b) {
15-
; CHECK-LABEL: whilewr_16:
16-
; CHECK: // %bb.0: // %entry
17-
; CHECK-NEXT: whilewr p0.h, x0, x1
18-
; CHECK-NEXT: ret
27+
; CHECK-SVE2-LABEL: whilewr_16:
28+
; CHECK-SVE2: // %bb.0: // %entry
29+
; CHECK-SVE2-NEXT: whilewr p0.h, x0, x1
30+
; CHECK-SVE2-NEXT: ret
31+
;
32+
; CHECK-SVE-LABEL: whilewr_16:
33+
; CHECK-SVE: // %bb.0: // %entry
34+
; CHECK-SVE-NEXT: sub x8, x1, x0
35+
; CHECK-SVE-NEXT: add x8, x8, x8, lsr #63
36+
; CHECK-SVE-NEXT: asr x8, x8, #1
37+
; CHECK-SVE-NEXT: cmp x8, #1
38+
; CHECK-SVE-NEXT: cset w9, lt
39+
; CHECK-SVE-NEXT: whilelo p0.h, #0, x8
40+
; CHECK-SVE-NEXT: sbfx x8, x9, #0, #1
41+
; CHECK-SVE-NEXT: whilelo p1.h, xzr, x8
42+
; CHECK-SVE-NEXT: sel p0.b, p0, p0.b, p1.b
43+
; CHECK-SVE-NEXT: ret
1944
entry:
2045
%0 = call <vscale x 8 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 2, i1 1)
2146
ret <vscale x 8 x i1> %0
2247
}
2348

2449
define <vscale x 4 x i1> @whilewr_32(i64 %a, i64 %b) {
25-
; CHECK-LABEL: whilewr_32:
26-
; CHECK: // %bb.0: // %entry
27-
; CHECK-NEXT: whilewr p0.s, x0, x1
28-
; CHECK-NEXT: ret
50+
; CHECK-SVE2-LABEL: whilewr_32:
51+
; CHECK-SVE2: // %bb.0: // %entry
52+
; CHECK-SVE2-NEXT: whilewr p0.s, x0, x1
53+
; CHECK-SVE2-NEXT: ret
54+
;
55+
; CHECK-SVE-LABEL: whilewr_32:
56+
; CHECK-SVE: // %bb.0: // %entry
57+
; CHECK-SVE-NEXT: sub x8, x1, x0
58+
; CHECK-SVE-NEXT: add x9, x8, #3
59+
; CHECK-SVE-NEXT: cmp x8, #0
60+
; CHECK-SVE-NEXT: csel x8, x9, x8, lt
61+
; CHECK-SVE-NEXT: asr x8, x8, #2
62+
; CHECK-SVE-NEXT: cmp x8, #1
63+
; CHECK-SVE-NEXT: cset w9, lt
64+
; CHECK-SVE-NEXT: whilelo p1.s, #0, x8
65+
; CHECK-SVE-NEXT: sbfx x9, x9, #0, #1
66+
; CHECK-SVE-NEXT: whilelo p0.s, xzr, x9
67+
; CHECK-SVE-NEXT: mov p0.b, p1/m, p1.b
68+
; CHECK-SVE-NEXT: ret
2969
entry:
3070
%0 = call <vscale x 4 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 4, i1 1)
3171
ret <vscale x 4 x i1> %0
3272
}
3373

3474
define <vscale x 2 x i1> @whilewr_64(i64 %a, i64 %b) {
35-
; CHECK-LABEL: whilewr_64:
36-
; CHECK: // %bb.0: // %entry
37-
; CHECK-NEXT: whilewr p0.d, x0, x1
38-
; CHECK-NEXT: ret
75+
; CHECK-SVE2-LABEL: whilewr_64:
76+
; CHECK-SVE2: // %bb.0: // %entry
77+
; CHECK-SVE2-NEXT: whilewr p0.d, x0, x1
78+
; CHECK-SVE2-NEXT: ret
79+
;
80+
; CHECK-SVE-LABEL: whilewr_64:
81+
; CHECK-SVE: // %bb.0: // %entry
82+
; CHECK-SVE-NEXT: sub x8, x1, x0
83+
; CHECK-SVE-NEXT: add x9, x8, #7
84+
; CHECK-SVE-NEXT: cmp x8, #0
85+
; CHECK-SVE-NEXT: csel x8, x9, x8, lt
86+
; CHECK-SVE-NEXT: asr x8, x8, #3
87+
; CHECK-SVE-NEXT: cmp x8, #1
88+
; CHECK-SVE-NEXT: cset w9, lt
89+
; CHECK-SVE-NEXT: whilelo p1.d, #0, x8
90+
; CHECK-SVE-NEXT: sbfx x9, x9, #0, #1
91+
; CHECK-SVE-NEXT: whilelo p0.d, xzr, x9
92+
; CHECK-SVE-NEXT: mov p0.b, p1/m, p1.b
93+
; CHECK-SVE-NEXT: ret
3994
entry:
4095
%0 = call <vscale x 2 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 8, i1 1)
4196
ret <vscale x 2 x i1> %0
4297
}
4398

4499
define <vscale x 16 x i1> @whilerw_8(i64 %a, i64 %b) {
45-
; CHECK-LABEL: whilerw_8:
46-
; CHECK: // %bb.0: // %entry
47-
; CHECK-NEXT: whilerw p0.b, x0, x1
48-
; CHECK-NEXT: ret
100+
; CHECK-SVE2-LABEL: whilerw_8:
101+
; CHECK-SVE2: // %bb.0: // %entry
102+
; CHECK-SVE2-NEXT: whilerw p0.b, x0, x1
103+
; CHECK-SVE2-NEXT: ret
104+
;
105+
; CHECK-SVE-LABEL: whilerw_8:
106+
; CHECK-SVE: // %bb.0: // %entry
107+
; CHECK-SVE-NEXT: subs x8, x1, x0
108+
; CHECK-SVE-NEXT: cneg x8, x8, mi
109+
; CHECK-SVE-NEXT: cmp x8, #0
110+
; CHECK-SVE-NEXT: cset w9, eq
111+
; CHECK-SVE-NEXT: whilelo p0.b, #0, x8
112+
; CHECK-SVE-NEXT: sbfx x8, x9, #0, #1
113+
; CHECK-SVE-NEXT: whilelo p1.b, xzr, x8
114+
; CHECK-SVE-NEXT: sel p0.b, p0, p0.b, p1.b
115+
; CHECK-SVE-NEXT: ret
49116
entry:
50117
%0 = call <vscale x 16 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 1, i1 0)
51118
ret <vscale x 16 x i1> %0
52119
}
53120

54121
define <vscale x 8 x i1> @whilerw_16(i64 %a, i64 %b) {
55-
; CHECK-LABEL: whilerw_16:
56-
; CHECK: // %bb.0: // %entry
57-
; CHECK-NEXT: whilerw p0.h, x0, x1
58-
; CHECK-NEXT: ret
122+
; CHECK-SVE2-LABEL: whilerw_16:
123+
; CHECK-SVE2: // %bb.0: // %entry
124+
; CHECK-SVE2-NEXT: whilerw p0.h, x0, x1
125+
; CHECK-SVE2-NEXT: ret
126+
;
127+
; CHECK-SVE-LABEL: whilerw_16:
128+
; CHECK-SVE: // %bb.0: // %entry
129+
; CHECK-SVE-NEXT: subs x8, x1, x0
130+
; CHECK-SVE-NEXT: cneg x8, x8, mi
131+
; CHECK-SVE-NEXT: add x8, x8, x8, lsr #63
132+
; CHECK-SVE-NEXT: asr x8, x8, #1
133+
; CHECK-SVE-NEXT: cmp x8, #0
134+
; CHECK-SVE-NEXT: cset w9, eq
135+
; CHECK-SVE-NEXT: whilelo p0.h, #0, x8
136+
; CHECK-SVE-NEXT: sbfx x8, x9, #0, #1
137+
; CHECK-SVE-NEXT: whilelo p1.h, xzr, x8
138+
; CHECK-SVE-NEXT: sel p0.b, p0, p0.b, p1.b
139+
; CHECK-SVE-NEXT: ret
59140
entry:
60141
%0 = call <vscale x 8 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 2, i1 0)
61142
ret <vscale x 8 x i1> %0
62143
}
63144

64145
define <vscale x 4 x i1> @whilerw_32(i64 %a, i64 %b) {
65-
; CHECK-LABEL: whilerw_32:
66-
; CHECK: // %bb.0: // %entry
67-
; CHECK-NEXT: whilerw p0.s, x0, x1
68-
; CHECK-NEXT: ret
146+
; CHECK-SVE2-LABEL: whilerw_32:
147+
; CHECK-SVE2: // %bb.0: // %entry
148+
; CHECK-SVE2-NEXT: whilerw p0.s, x0, x1
149+
; CHECK-SVE2-NEXT: ret
150+
;
151+
; CHECK-SVE-LABEL: whilerw_32:
152+
; CHECK-SVE: // %bb.0: // %entry
153+
; CHECK-SVE-NEXT: subs x8, x1, x0
154+
; CHECK-SVE-NEXT: cneg x8, x8, mi
155+
; CHECK-SVE-NEXT: add x9, x8, #3
156+
; CHECK-SVE-NEXT: cmp x8, #0
157+
; CHECK-SVE-NEXT: csel x8, x9, x8, lt
158+
; CHECK-SVE-NEXT: asr x8, x8, #2
159+
; CHECK-SVE-NEXT: cmp x8, #0
160+
; CHECK-SVE-NEXT: cset w9, eq
161+
; CHECK-SVE-NEXT: whilelo p1.s, #0, x8
162+
; CHECK-SVE-NEXT: sbfx x9, x9, #0, #1
163+
; CHECK-SVE-NEXT: whilelo p0.s, xzr, x9
164+
; CHECK-SVE-NEXT: mov p0.b, p1/m, p1.b
165+
; CHECK-SVE-NEXT: ret
69166
entry:
70167
%0 = call <vscale x 4 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 4, i1 0)
71168
ret <vscale x 4 x i1> %0
72169
}
73170

74171
define <vscale x 2 x i1> @whilerw_64(i64 %a, i64 %b) {
75-
; CHECK-LABEL: whilerw_64:
76-
; CHECK: // %bb.0: // %entry
77-
; CHECK-NEXT: whilerw p0.d, x0, x1
78-
; CHECK-NEXT: ret
172+
; CHECK-SVE2-LABEL: whilerw_64:
173+
; CHECK-SVE2: // %bb.0: // %entry
174+
; CHECK-SVE2-NEXT: whilerw p0.d, x0, x1
175+
; CHECK-SVE2-NEXT: ret
176+
;
177+
; CHECK-SVE-LABEL: whilerw_64:
178+
; CHECK-SVE: // %bb.0: // %entry
179+
; CHECK-SVE-NEXT: subs x8, x1, x0
180+
; CHECK-SVE-NEXT: cneg x8, x8, mi
181+
; CHECK-SVE-NEXT: add x9, x8, #7
182+
; CHECK-SVE-NEXT: cmp x8, #0
183+
; CHECK-SVE-NEXT: csel x8, x9, x8, lt
184+
; CHECK-SVE-NEXT: asr x8, x8, #3
185+
; CHECK-SVE-NEXT: cmp x8, #0
186+
; CHECK-SVE-NEXT: cset w9, eq
187+
; CHECK-SVE-NEXT: whilelo p1.d, #0, x8
188+
; CHECK-SVE-NEXT: sbfx x9, x9, #0, #1
189+
; CHECK-SVE-NEXT: whilelo p0.d, xzr, x9
190+
; CHECK-SVE-NEXT: mov p0.b, p1/m, p1.b
191+
; CHECK-SVE-NEXT: ret
79192
entry:
80193
%0 = call <vscale x 2 x i1> @llvm.experimental.get.alias.lane.mask.v8i1.i64.i64(i64 %a, i64 %b, i64 8, i1 0)
81194
ret <vscale x 2 x i1> %0

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