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[AArch64] Add initial support for -mcpu=olympus. (#132368)
This patch adds support for the NVIDIA Olympus core. This does not add any special tuning decisions, and those may come later.
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‎clang/test/Driver/aarch64-nvidia-olympus.c

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// RUN: %clang --target=aarch64 -mcpu=olympus -### -c %s 2>&1 | FileCheck -check-prefix=olympus %s
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// RUN: %clang --target=aarch64 -mlittle-endian -mcpu=olympus -### -c %s 2>&1 | FileCheck -check-prefix=olympus %s
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// RUN: %clang --target=aarch64 -mtune=olympus -### -c %s 2>&1 | FileCheck -check-prefix=olympus-TUNE %s
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// RUN: %clang --target=aarch64 -mlittle-endian -mtune=olympus -### -c %s 2>&1 | FileCheck -check-prefix=olympus-TUNE %s
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// olympus: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "olympus"
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// olympus-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
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// RUN: %clang --target=arm64 -mcpu=olympus -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-olympus %s
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// RUN: %clang --target=arm64 -mlittle-endian -mcpu=olympus -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-olympus %s
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// RUN: %clang --target=arm64 -mtune=olympus -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-olympus-TUNE %s
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// RUN: %clang --target=arm64 -mlittle-endian -mtune=olympus -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-olympus-TUNE %s
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// ARM64-olympus: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "olympus"
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// ARM64-olympus-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"

‎clang/test/Driver/print-enabled-extensions/aarch64-olympus.c

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// REQUIRES: aarch64-registered-target
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// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=olympus | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: Extensions enabled for the given AArch64 target
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// CHECK-EMPTY:
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// CHECK-NEXT: Architecture Feature(s) Description
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// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
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// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
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// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
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// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
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// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
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// CHECK-NEXT: FEAT_BRBE Enable Branch Record Buffer Extension
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// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
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// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
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// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension
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// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
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// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
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// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
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// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
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// CHECK-NEXT: FEAT_DotProd Enable dot product support
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// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
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// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
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// CHECK-NEXT: FEAT_FAMINMAX Enable FAMIN and FAMAX instructions
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// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FP8 Enable FP8 instructions
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// CHECK-NEXT: FEAT_FP8DOT2 Enable FP8 2-way dot instructions
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// CHECK-NEXT: FEAT_FP8DOT4 Enable FP8 4-way dot instructions
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// CHECK-NEXT: FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions
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// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
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// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
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// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
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// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
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// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
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// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
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// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
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// CHECK-NEXT: FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
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// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
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// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
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// CHECK-NEXT: FEAT_LUT Enable Lookup Table instructions
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// CHECK-NEXT: FEAT_MEC Enable Memory Encryption Contexts Extension
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// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
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// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
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// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
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// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
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// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
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// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
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// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
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// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
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// CHECK-NEXT: FEAT_RME Enable Realm Management Extension
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// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
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// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
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// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
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// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
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// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
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// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
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// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
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// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
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// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
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// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction

‎clang/test/Misc/target-invalid-cpu-note/aarch64.c

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// CHECK-SAME: {{^}}, neoverse-v2
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// CHECK-SAME: {{^}}, neoverse-v3
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// CHECK-SAME: {{^}}, neoverse-v3ae
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// CHECK-SAME: {{^}}, olympus
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// CHECK-SAME: {{^}}, oryon-1
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// CHECK-SAME: {{^}}, saphira
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// CHECK-SAME: {{^}}, thunderx

‎llvm/lib/Target/AArch64/AArch64Processors.td

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@@ -284,6 +284,17 @@ def TuneMONAKA : SubtargetFeature<"fujitsu-monaka", "ARMProcFamily", "MONAKA",
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def TuneCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
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"Nvidia Carmel processors">;
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def TuneOlympus : SubtargetFeature<"olympus", "ARMProcFamily", "Olympus",
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"NVIDIA Olympus processors", [
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FeatureALULSLFast,
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FeatureCmpBccFusion,
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FeatureEnableSelectOptimize,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureUseFixedOverScalableIfEqualCost]>;
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// Note that cyclone does not fuse AES instructions, but newer apple chips do
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// perform the fusion and cyclone is used by default when targetting apple OSes.
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def TuneAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
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list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES,
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FeatureFullFP16, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM,
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FeatureFPARMv8];
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list<SubtargetFeature> Olympus = [HasV9_2aOps, FeatureBRBE, FeatureCCIDX,
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FeatureCHK, FeatureETE, FeatureFAMINMAX,
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FeatureFP16FML, FeatureFP8DOT2,
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FeatureFP8DOT4, FeatureFP8FMA, FeatureFPAC,
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FeatureLS64, FeatureLUT, FeatureMEC,
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FeatureMTE, FeaturePerfMon, FeatureRandGen,
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FeatureSPE, FeatureSPE_EEF, FeatureSSBS,
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FeatureSVEBitPerm, FeatureSVE2SHA3,
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FeatureSVE2SM4, FeatureSVEAES];
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list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
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FeatureNEON,FeaturePerfMon];
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list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
@@ -1266,6 +1286,10 @@ def : ProcessorModel<"fujitsu-monaka", A64FXModel, ProcessorFeatures.MONAKA,
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def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel,
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[TuneCarmel]>;
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// NVIDIA Olympus
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def : ProcessorModel<"olympus", NeoverseV2Model, ProcessorFeatures.Olympus,
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[TuneOlympus]>;
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// Ampere Computing
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def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
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[TuneAmpere1]>;

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

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@@ -349,6 +349,15 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
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PrefetchDistance = 128;
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MinPrefetchStride = 1024;
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break;
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case Olympus:
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EpilogueVectorizationMinVF = 8;
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MaxInterleaveFactor = 4;
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ScatterOverhead = 13;
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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VScaleForTuning = 1;
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break;
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}
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if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize)

‎llvm/lib/TargetParser/Host.cpp

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@@ -288,6 +288,8 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
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if (Implementer == "0x4e") { // NVIDIA Corporation
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return StringSwitch<const char *>(Part)
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.Case("0x004", "carmel")
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.Case("0x10", "olympus")
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.Case("0x010", "olympus")
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.Default("generic");
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}
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‎llvm/test/CodeGen/AArch64/cpus.ll

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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=carmel 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=olympus 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a34 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s

‎llvm/unittests/TargetParser/Host.cpp

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EXPECT_EQ(sys::detail::getHostCPUNameForARM(CarmelProcCpuInfo), "carmel");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x4e\n"
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"CPU part : 0x10"),
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"olympus");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x4e\n"
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"CPU part : 0x010"),
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"olympus");
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// Snapdragon mixed implementer quirk
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const std::string Snapdragon865ProcCPUInfo = R"(
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processor : 0

‎llvm/unittests/TargetParser/TargetParserTest.cpp

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@@ -1168,6 +1168,7 @@ INSTANTIATE_TEST_SUITE_P(
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AArch64CPUTestParams("fujitsu-monaka", "armv9.3-a"),
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AArch64CPUTestParams("carmel", "armv8.2-a"),
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AArch64CPUTestParams("grace", "armv9-a"),
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AArch64CPUTestParams("olympus", "armv9.2-a"),
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AArch64CPUTestParams("saphira", "armv8.4-a"),
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AArch64CPUTestParams("oryon-1", "armv8.6-a")),
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AArch64CPUTestParams::PrintToStringParamName);
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AArch64CPUAliasTestParams::PrintToStringParamName);
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// Note: number of CPUs includes aliases.
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static constexpr unsigned NumAArch64CPUArchs = 88;
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static constexpr unsigned NumAArch64CPUArchs = 89;
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TEST(TargetParserTest, testAArch64CPUArchList) {
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SmallVector<StringRef, NumAArch64CPUArchs> List;

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