@@ -7,17 +7,15 @@ target triple = "nvptx64-nvidia-cuda"
7
7
define i1 @and_ord (float %a , float %b ) {
8
8
; CHECK-LABEL: and_ord(
9
9
; CHECK: {
10
- ; CHECK-NEXT: .reg .pred %p<4 >;
10
+ ; CHECK-NEXT: .reg .pred %p<2 >;
11
11
; CHECK-NEXT: .reg .b32 %r<2>;
12
12
; CHECK-NEXT: .reg .f32 %f<3>;
13
13
; CHECK-EMPTY:
14
14
; CHECK-NEXT: // %bb.0:
15
15
; CHECK-NEXT: ld.param.f32 %f1, [and_ord_param_0];
16
- ; CHECK-NEXT: setp.num.f32 %p1, %f1, %f1;
17
16
; CHECK-NEXT: ld.param.f32 %f2, [and_ord_param_1];
18
- ; CHECK-NEXT: setp.num.f32 %p2, %f2, %f2;
19
- ; CHECK-NEXT: and.pred %p3, %p1, %p2;
20
- ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p3;
17
+ ; CHECK-NEXT: setp.num.f32 %p1, %f1, %f2;
18
+ ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
21
19
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
22
20
; CHECK-NEXT: ret;
23
21
%c = fcmp ord float %a , 0 .0
@@ -29,17 +27,15 @@ define i1 @and_ord(float %a, float %b) {
29
27
define i1 @or_uno (float %a , float %b ) {
30
28
; CHECK-LABEL: or_uno(
31
29
; CHECK: {
32
- ; CHECK-NEXT: .reg .pred %p<4 >;
30
+ ; CHECK-NEXT: .reg .pred %p<2 >;
33
31
; CHECK-NEXT: .reg .b32 %r<2>;
34
32
; CHECK-NEXT: .reg .f32 %f<3>;
35
33
; CHECK-EMPTY:
36
34
; CHECK-NEXT: // %bb.0:
37
35
; CHECK-NEXT: ld.param.f32 %f1, [or_uno_param_0];
38
- ; CHECK-NEXT: setp.nan.f32 %p1, %f1, %f1;
39
36
; CHECK-NEXT: ld.param.f32 %f2, [or_uno_param_1];
40
- ; CHECK-NEXT: setp.nan.f32 %p2, %f2, %f2;
41
- ; CHECK-NEXT: or.pred %p3, %p1, %p2;
42
- ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p3;
37
+ ; CHECK-NEXT: setp.nan.f32 %p1, %f1, %f2;
38
+ ; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
43
39
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
44
40
; CHECK-NEXT: ret;
45
41
%c = fcmp uno float %a , 0 .0
0 commit comments