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[RISCV] Update SiFive P600's scheduling model on RVV instructions (#115243)
The biggest change is assigning vector crypto instructions to the correct processor resource. The majority of these changes are guided by our RVV-capable llvm-exegesis.
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‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

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‎llvm/test/tools/llvm-mca/RISCV/SiFiveP600/mask.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=100 < %s | FileCheck %s
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vsetvli zero, zero, e32, m1, ta, ma
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vmslt.vv v0, v4, v20
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vmsle.vv v8, v4, v20
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vmsgt.vv v8, v20, v4
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vmsge.vv v8, v20, v4
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vmseq.vv v8, v4, v20
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vmsne.vv v8, v4, v20
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vmsltu.vv v8, v4, v20
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vmsleu.vv v8, v4, v20
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vmsgtu.vv v8, v20, v4
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vmsgeu.vv v8, v20, v4
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vmflt.vv v0, v4, v20
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vmfle.vv v8, v4, v20
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vmfgt.vv v8, v20, v4
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vmfge.vv v8, v20, v4
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vmfeq.vv v8, v4, v20
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vmfne.vv v8, v4, v20
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vmadc.vv v8, v4, v20
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vmsbc.vv v8, v4, v20
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vfirst.m a2, v4
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vpopc.m a2, v4
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viota.m v8, v4
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vmsbf.m v8, v4
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vmsif.m v8, v4
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vmsof.m v8, v4
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# CHECK: Iterations: 100
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# CHECK-NEXT: Instructions: 2500
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# CHECK-NEXT: Total Cycles: 2605
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# CHECK-NEXT: Total uOps: 2500
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# CHECK: Dispatch Width: 4
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# CHECK-NEXT: uOps Per Cycle: 0.96
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# CHECK-NEXT: IPC: 0.96
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# CHECK-NEXT: Block RThroughput: 26.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
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# CHECK-NEXT: 1 2 1.00 vmslt.vv v0, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsle.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmslt.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsle.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmseq.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsne.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsltu.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsleu.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsltu.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsleu.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmflt.vv v0, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmfle.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmflt.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmfle.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmfeq.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmfne.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmadc.vv v8, v4, v20
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# CHECK-NEXT: 1 2 1.00 vmsbc.vv v8, v4, v20
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# CHECK-NEXT: 1 2 2.00 vfirst.m a2, v4
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# CHECK-NEXT: 1 2 2.00 vcpop.m a2, v4
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# CHECK-NEXT: 1 2 1.00 viota.m v8, v4
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# CHECK-NEXT: 1 2 1.00 vmsbf.m v8, v4
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# CHECK-NEXT: 1 2 1.00 vmsif.m v8, v4
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# CHECK-NEXT: 1 2 1.00 vmsof.m v8, v4
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP600Div
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# CHECK-NEXT: [1] - SiFiveP600FEXQ0
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# CHECK-NEXT: [2] - SiFiveP600FEXQ1
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# CHECK-NEXT: [3] - SiFiveP600FloatDiv
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# CHECK-NEXT: [4] - SiFiveP600IEXQ0
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# CHECK-NEXT: [5] - SiFiveP600IEXQ1
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# CHECK-NEXT: [6] - SiFiveP600IEXQ2
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# CHECK-NEXT: [7] - SiFiveP600IEXQ3
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# CHECK-NEXT: [8.0] - SiFiveP600LDST
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# CHECK-NEXT: [8.1] - SiFiveP600LDST
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# CHECK-NEXT: [9] - SiFiveP600VDiv
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# CHECK-NEXT: [10] - SiFiveP600VEXQ0
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# CHECK-NEXT: [11] - SiFiveP600VEXQ1
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# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
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# CHECK-NEXT: [13] - SiFiveP600VLD
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# CHECK-NEXT: [14] - SiFiveP600VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
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# CHECK-NEXT: - - - - 1.00 - - - - - - 26.00 - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
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# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v0, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmslt.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsle.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmseq.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsne.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsleu.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsltu.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsleu.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmflt.vv v0, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmflt.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfle.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfeq.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmfne.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmadc.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsbc.vv v8, v4, v20
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# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vfirst.m a2, v4
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# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vcpop.m a2, v4
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - viota.m v8, v4
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsbf.m v8, v4
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsif.m v8, v4
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# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vmsof.m v8, v4

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