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[RISCV][VP] Introduce vp saturating addition/subtraction and RISC-V support. (#82370)
This patch also pick the MatchContext framework from DAGCombiner to an indiviual header file to make the framework be used from other files in llvm/lib/CodeGen/SelectionDAG/.
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‎llvm/docs/LangRef.rst

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@@ -16749,6 +16749,7 @@ an operation is greater than the maximum value, the result is set (or
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"clamped") to this maximum. If it is below the minimum, it is clamped to this
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minimum.
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.. _int_sadd_sat:
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'``llvm.sadd.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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%res = call i4 @llvm.sadd.sat.i4(i4 -4, i4 -5) ; %res = -8
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.. _int_uadd_sat:
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'``llvm.uadd.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -16845,6 +16848,8 @@ Examples
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%res = call i4 @llvm.uadd.sat.i4(i4 8, i4 8) ; %res = 15
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.. _int_ssub_sat:
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'``llvm.ssub.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -16893,6 +16898,8 @@ Examples
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%res = call i4 @llvm.ssub.sat.i4(i4 4, i4 -5) ; %res = 7
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.. _int_usub_sat:
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'``llvm.usub.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@@ -23610,6 +23617,202 @@ Examples:
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_sadd_sat:
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'``llvm.vp.sadd.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.sadd.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
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declare <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
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declare <256 x i64> @llvm.vp.sadd.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
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Overview:
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"""""""""
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Predicated signed saturating addition of two vectors of integers.
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Arguments:
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""""""""""
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The first two operands and the result have the same vector of integer type. The
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third operand is the vector mask and has the same number of elements as the
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result vector type. The fourth operand is the explicit vector length of the
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operation.
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Semantics:
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""""""""""
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The '``llvm.vp.sadd.sat``' intrinsic performs sadd.sat (:ref:`sadd.sat <int_sadd_sat>`)
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of the first and second vector operands on each enabled lane. The result on
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disabled lanes is a :ref:`poison value <poisonvalues>`.
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Examples:
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"""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
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;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
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%t = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_uadd_sat:
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'``llvm.vp.uadd.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.uadd.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
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declare <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
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declare <256 x i64> @llvm.vp.uadd.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
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Overview:
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"""""""""
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Predicated unsigned saturating addition of two vectors of integers.
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Arguments:
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""""""""""
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The first two operands and the result have the same vector of integer type. The
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third operand is the vector mask and has the same number of elements as the
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result vector type. The fourth operand is the explicit vector length of the
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operation.
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Semantics:
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""""""""""
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The '``llvm.vp.uadd.sat``' intrinsic performs uadd.sat (:ref:`uadd.sat <int_uadd_sat>`)
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of the first and second vector operands on each enabled lane. The result on
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disabled lanes is a :ref:`poison value <poisonvalues>`.
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Examples:
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"""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
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;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
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%t = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_ssub_sat:
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'``llvm.vp.ssub.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.ssub.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
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declare <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
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declare <256 x i64> @llvm.vp.ssub.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
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Overview:
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"""""""""
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Predicated signed saturating subtraction of two vectors of integers.
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Arguments:
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""""""""""
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The first two operands and the result have the same vector of integer type. The
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third operand is the vector mask and has the same number of elements as the
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result vector type. The fourth operand is the explicit vector length of the
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operation.
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Semantics:
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""""""""""
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The '``llvm.vp.ssub.sat``' intrinsic performs ssub.sat (:ref:`ssub.sat <int_ssub_sat>`)
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of the first and second vector operands on each enabled lane. The result on
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disabled lanes is a :ref:`poison value <poisonvalues>`.
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Examples:
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"""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
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;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
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%t = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_usub_sat:
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'``llvm.vp.usub.sat.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <16 x i32> @llvm.vp.usub.sat.v16i32 (<16 x i32> <left_op> <16 x i32> <right_op>, <16 x i1> <mask>, i32 <vector_length>)
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declare <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32 (<vscale x 4 x i32> <left_op>, <vscale x 4 x i32> <right_op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
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declare <256 x i64> @llvm.vp.usub.sat.v256i64 (<256 x i64> <left_op>, <256 x i64> <right_op>, <256 x i1> <mask>, i32 <vector_length>)
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Overview:
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"""""""""
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Predicated unsigned saturating subtraction of two vectors of integers.
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Arguments:
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""""""""""
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The first two operands and the result have the same vector of integer type. The
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third operand is the vector mask and has the same number of elements as the
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result vector type. The fourth operand is the explicit vector length of the
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operation.
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Semantics:
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""""""""""
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The '``llvm.vp.usub.sat``' intrinsic performs usub.sat (:ref:`usub.sat <int_usub_sat>`)
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of the first and second vector operands on each enabled lane. The result on
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disabled lanes is a :ref:`poison value <poisonvalues>`.
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Examples:
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"""""""""
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.. code-block:: llvm
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%r = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %mask, i32 %evl)
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;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
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%t = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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%also.r = select <4 x i1> %mask, <4 x i32> %t, <4 x i32> poison
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.. _int_vp_fshl:
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'``llvm.vp.fshl.*``' Intrinsics

‎llvm/include/llvm/IR/Intrinsics.td

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@@ -1933,6 +1933,26 @@ let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in {
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_sadd_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_uadd_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_ssub_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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def int_vp_usub_sat : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
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[ LLVMMatchType<0>,
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LLVMMatchType<0>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
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llvm_i32_ty]>;
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// Floating-point arithmetic
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def int_vp_fadd : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],

‎llvm/include/llvm/IR/VPIntrinsics.def

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@@ -293,6 +293,30 @@ BEGIN_REGISTER_VP(vp_fshr, 3, 4, VP_FSHR, -1)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(fshr)
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VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
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END_REGISTER_VP(vp_fshr, VP_FSHR)
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// llvm.vp.sadd.sat(x,y,mask,vlen)
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BEGIN_REGISTER_VP(vp_sadd_sat, 2, 3, VP_SADDSAT, -1)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(sadd_sat)
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VP_PROPERTY_FUNCTIONAL_SDOPC(SADDSAT)
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END_REGISTER_VP(vp_sadd_sat, VP_SADDSAT)
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// llvm.vp.uadd.sat(x,y,mask,vlen)
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BEGIN_REGISTER_VP(vp_uadd_sat, 2, 3, VP_UADDSAT, -1)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(uadd_sat)
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VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
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END_REGISTER_VP(vp_uadd_sat, VP_UADDSAT)
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// llvm.vp.ssub.sat(x,y,mask,vlen)
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BEGIN_REGISTER_VP(vp_ssub_sat, 2, 3, VP_SSUBSAT, -1)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(ssub_sat)
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VP_PROPERTY_FUNCTIONAL_SDOPC(SSUBSAT)
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END_REGISTER_VP(vp_ssub_sat, VP_SSUBSAT)
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// llvm.vp.usub.sat(x,y,mask,vlen)
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BEGIN_REGISTER_VP(vp_usub_sat, 2, 3, VP_USUBSAT, -1)
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VP_PROPERTY_FUNCTIONAL_INTRINSIC(usub_sat)
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VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
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END_REGISTER_VP(vp_usub_sat, VP_USUBSAT)
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///// } Integer Arithmetic
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///// Floating-Point Arithmetic {

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