Skip to content

Commit 8545659

Browse files
committed
Don't check ratio
1 parent 5b29e16 commit 8545659

File tree

1 file changed

+15
-27
lines changed

1 file changed

+15
-27
lines changed

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

Lines changed: 15 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ class RISCVVectorPeephole : public MachineFunctionPass {
6969
bool foldUndefPassthruVMV_V_V(MachineInstr &MI);
7070
bool foldVMV_V_V(MachineInstr &MI);
7171

72-
bool hasSameEEWVLMAX(const MachineInstr &User, const MachineInstr &Src) const;
72+
bool hasSameEEW(const MachineInstr &User, const MachineInstr &Src) const;
7373
bool isAllOnesMask(const MachineInstr *MaskDef) const;
7474
std::optional<unsigned> getConstant(const MachineOperand &VL) const;
7575
bool ensureDominates(const MachineOperand &Use, MachineInstr &Src) const;
@@ -99,28 +99,17 @@ static bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
9999
return LHS.getImm() <= RHS.getImm();
100100
}
101101

102-
static unsigned getSEWLMULRatio(const MachineInstr &MI) {
103-
RISCVII::VLMUL LMUL = RISCVII::getLMul(MI.getDesc().TSFlags);
104-
unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
105-
return RISCVVType::getSEWLMULRatio(1 << Log2SEW, LMUL);
106-
}
107-
108-
/// Given \p User that has an input operand with EEW=SEW, which uses an output
109-
/// operand of \p Src with an unknown EEW, return true if their EEWs match and
110-
/// they have the same VLMAX.
111-
bool RISCVVectorPeephole::hasSameEEWVLMAX(const MachineInstr &User,
112-
const MachineInstr &Src) const {
113-
if (getSEWLMULRatio(User) != getSEWLMULRatio(Src))
114-
return false;
115-
unsigned UserLog2SEW =
102+
/// Given \p User that has an input operand with EEW=SEW, which uses the dest
103+
/// operand of \p Src with an unknown EEW, return true if their EEWs match.
104+
bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
105+
const MachineInstr &Src) const {
106+
unsigned UserSEW =
116107
User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
117-
unsigned SrcLog2SEW =
108+
unsigned SrcSEW =
118109
Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm();
119-
if (RISCV::getDestEEW(TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())),
120-
SrcLog2SEW) != UserLog2SEW)
121-
return false;
122-
123-
return true;
110+
unsigned SrcEEW = RISCV::getDestEEW(
111+
TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcSEW);
112+
return SrcEEW == UserSEW;
124113
}
125114

126115
// Attempt to reduce the VL of an instruction whose sole use is feeding a
@@ -173,8 +162,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
173162
!RISCVII::hasSEWOp(Src->getDesc().TSFlags))
174163
return false;
175164

176-
// Src needs to have the same VLMAX and EEW as MI
177-
if (!hasSameEEWVLMAX(MI, *Src))
165+
// Src's dest needs to have the same EEW as MI's input.
166+
if (!hasSameEEW(MI, *Src))
178167
return false;
179168

180169
bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
@@ -505,8 +494,7 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
505494
if (Src && !Src->hasUnmodeledSideEffects() &&
506495
MRI->hasOneUse(MI.getOperand(2).getReg()) &&
507496
RISCVII::hasVLOp(Src->getDesc().TSFlags) &&
508-
RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags) &&
509-
hasSameEEWVLMAX(MI, *Src)) {
497+
RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags) && hasSameEEW(MI, *Src)) {
510498
const MachineOperand &MIVL = MI.getOperand(3);
511499
const MachineOperand &SrcVL =
512500
Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
@@ -551,8 +539,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
551539
!RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags))
552540
return false;
553541

554-
// Src needs to have the same VLMAX and EEW as MI
555-
if (!hasSameEEWVLMAX(MI, *Src))
542+
// Src's dest needs to have the same EEW as MI's input.
543+
if (!hasSameEEW(MI, *Src))
556544
return false;
557545

558546
// Src needs to have the same passthru as VMV_V_V

0 commit comments

Comments
 (0)