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[RISCV] Rename $merge to $rd in Zvk* pseudoinstructions and patterns.
These instructions use the destination operand as a source, not only as a passthru for mask/tail.
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llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -181,13 +181,13 @@ class ZvkMxSet<string vd_lmul> {
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}
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class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
184-
Pseudo<(outs RetClass:$rd),
185-
(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
184+
Pseudo<(outs RetClass:$rd_wb),
185+
(ins RetClass:$rd, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let Constraints = "$rd = $merge";
190+
let Constraints = "$rd_wb = $rd";
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let HasVLOp = 1;
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let HasSEWOp = 1;
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let HasVecPolicyOp = 1;
@@ -197,14 +197,14 @@ class VPseudoUnaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
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class VPseudoBinaryNoMask_Zvk<VReg RetClass,
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VReg Op1Class,
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DAGOperand Op2Class> :
200-
Pseudo<(outs RetClass:$rd),
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(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1,
200+
Pseudo<(outs RetClass:$rd_wb),
201+
(ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
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AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
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RISCVVPseudo {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
207-
let Constraints = "$rd = $merge";
207+
let Constraints = "$rd_wb = $rd";
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let HasVLOp = 1;
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let HasSEWOp = 1;
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let HasVecPolicyOp = 1;
@@ -670,11 +670,11 @@ class VPatUnaryNoMask_Zvk<string intrinsic_name,
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VReg result_reg_class,
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VReg op2_reg_class> :
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Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
673-
(result_type result_reg_class:$merge),
673+
(result_type result_reg_class:$rd),
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(op2_type op2_reg_class:$rs2),
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VLOpFrag, (XLenVT timm:$policy))),
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(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
677-
(result_type result_reg_class:$merge),
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(result_type result_reg_class:$rd),
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(op2_type op2_reg_class:$rs2),
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GPR:$vl, sew, (XLenVT timm:$policy))>;
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@@ -689,11 +689,11 @@ class VPatUnaryNoMask_VS_Zvk<string intrinsic_name,
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VReg result_reg_class,
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VReg op2_reg_class> :
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Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
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(result_type result_reg_class:$merge),
692+
(result_type result_reg_class:$rd),
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(op2_type op2_reg_class:$rs2),
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VLOpFrag, (XLenVT timm:$policy))),
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(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_"#vs2_lmul.MX)
696-
(result_type result_reg_class:$merge),
696+
(result_type result_reg_class:$rd),
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(op2_type op2_reg_class:$rs2),
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GPR:$vl, sew, (XLenVT timm:$policy))>;
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