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AArch64: Add FMINNUM_IEEE and FMAXNUM_IEEE support
FMINNM/FMAXNM instructions of AArch64 follow IEEE754-2008. We can use them to canonicalize a floating point number. And FMINNUM_IEEE/FMAXNUM_IEEE is used by something like expanding FMINIMUMNUM/FMAXIMUMNUM, so let's define them. Update combine_andor_with_cmps.ll. Add fp-maximumnum-minimumnum.ll, with nnan testcases only.
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -860,12 +860,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
860860
setOperationAction(ISD::FP_ROUND, MVT::v4bf16, Custom);
861861

862862
// AArch64 has implementations of a lot of rounding-like FP operations.
863+
// clang-format off
863864
for (auto Op :
864865
{ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL,
865866
ISD::FRINT, ISD::FTRUNC, ISD::FROUND,
866867
ISD::FROUNDEVEN, ISD::FMINNUM, ISD::FMAXNUM,
867868
ISD::FMINIMUM, ISD::FMAXIMUM, ISD::LROUND,
868869
ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
870+
ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
869871
ISD::STRICT_FFLOOR, ISD::STRICT_FCEIL, ISD::STRICT_FNEARBYINT,
870872
ISD::STRICT_FRINT, ISD::STRICT_FTRUNC, ISD::STRICT_FROUNDEVEN,
871873
ISD::STRICT_FROUND, ISD::STRICT_FMINNUM, ISD::STRICT_FMAXNUM,
@@ -876,6 +878,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
876878
if (Subtarget->hasFullFP16())
877879
setOperationAction(Op, MVT::f16, Legal);
878880
}
881+
// clang-format on
879882

880883
// Basic strict FP operations are legal
881884
for (auto Op : {ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
@@ -1201,6 +1204,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
12011204
ISD::STRICT_FMINIMUM, ISD::STRICT_FMAXIMUM})
12021205
setOperationAction(Op, MVT::v1f64, Expand);
12031206
// clang-format on
1207+
1208+
for (auto Op : {ISD::FMAXNUM_IEEE, ISD::FMINNUM_IEEE})
1209+
setOperationAction(Op, MVT::v1f64, Legal);
1210+
12041211
for (auto Op :
12051212
{ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP,
12061213
ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL,
@@ -1345,11 +1352,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
13451352
}
13461353

13471354
// AArch64 has implementations of a lot of rounding-like FP operations.
1355+
// And the same for FMAXNUM_IEEE and FMINNUM_IEEE.
13481356
for (auto Op :
13491357
{ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
1350-
ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR,
1351-
ISD::STRICT_FNEARBYINT, ISD::STRICT_FCEIL, ISD::STRICT_FRINT,
1352-
ISD::STRICT_FTRUNC, ISD::STRICT_FROUND, ISD::STRICT_FROUNDEVEN}) {
1358+
ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR, ISD::FMAXNUM_IEEE,
1359+
ISD::FMINNUM_IEEE, ISD::STRICT_FNEARBYINT, ISD::STRICT_FCEIL,
1360+
ISD::STRICT_FRINT, ISD::STRICT_FTRUNC, ISD::STRICT_FROUND,
1361+
ISD::STRICT_FROUNDEVEN}) {
13531362
for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64})
13541363
setOperationAction(Op, Ty, Legal);
13551364
if (Subtarget->hasFullFP16())

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5071,6 +5071,23 @@ def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
50715071
def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
50725072
(FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
50735073

5074+
def : Pat<(v1f64 (fmaxnum_ieee (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5075+
(FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
5076+
def : Pat<(v1f64 (fminnum_ieee (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5077+
(FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
5078+
def : Pat<(fminnum_ieee (f64 FPR64:$a), (f64 FPR64:$b)),
5079+
(FMINNMDrr FPR64:$a, FPR64:$b)>;
5080+
def : Pat<(fminnum_ieee (f32 FPR32:$a), (f32 FPR32:$b)),
5081+
(FMINNMSrr FPR32:$a, FPR32:$b)>;
5082+
def : Pat<(fminnum_ieee (f16 FPR16:$a), (f16 FPR16:$b)),
5083+
(FMINNMHrr FPR16:$a, FPR16:$b)>;
5084+
def : Pat<(fmaxnum_ieee (f64 FPR64:$a), (f64 FPR64:$b)),
5085+
(FMAXNMDrr FPR64:$a, FPR64:$b)>;
5086+
def : Pat<(fmaxnum_ieee (f32 FPR32:$a), (f32 FPR32:$b)),
5087+
(FMAXNMSrr FPR32:$a, FPR32:$b)>;
5088+
def : Pat<(fmaxnum_ieee (f16 FPR16:$a), (f16 FPR16:$b)),
5089+
(FMAXNMHrr FPR16:$a, FPR16:$b)>;
5090+
50745091
//===----------------------------------------------------------------------===//
50755092
// Floating point three operand instructions.
50765093
//===----------------------------------------------------------------------===//
@@ -5563,6 +5580,27 @@ defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", any_fminnum>;
55635580
defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;
55645581
defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", any_fminimum>;
55655582

5583+
def : Pat<(v2f64 (fminnum_ieee (v2f64 V128:$Rn), (v2f64 V128:$Rm))),
5584+
(v2f64 (FMINNMv2f64 (v2f64 V128:$Rn), (v2f64 V128:$Rm)))>;
5585+
def : Pat<(v4f32 (fminnum_ieee (v4f32 V128:$Rn), (v4f32 V128:$Rm))),
5586+
(v4f32 (FMINNMv4f32 (v4f32 V128:$Rn), (v4f32 V128:$Rm)))>;
5587+
def : Pat<(v8f16 (fminnum_ieee (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
5588+
(v8f16 (FMINNMv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm)))>;
5589+
def : Pat<(v2f32 (fminnum_ieee (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
5590+
(v2f32 (FMINNMv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm)))>;
5591+
def : Pat<(v4f16 (fminnum_ieee (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
5592+
(v4f16 (FMINNMv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm)))>;
5593+
def : Pat<(v2f64 (fmaxnum_ieee (v2f64 V128:$Rn), (v2f64 V128:$Rm))),
5594+
(v2f64 (FMAXNMv2f64 (v2f64 V128:$Rn), (v2f64 V128:$Rm)))>;
5595+
def : Pat<(v4f32 (fmaxnum_ieee (v4f32 V128:$Rn), (v4f32 V128:$Rm))),
5596+
(v4f32 (FMAXNMv4f32 (v4f32 V128:$Rn), (v4f32 V128:$Rm)))>;
5597+
def : Pat<(v8f16 (fmaxnum_ieee (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
5598+
(v8f16 (FMAXNMv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm)))>;
5599+
def : Pat<(v2f32 (fmaxnum_ieee (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
5600+
(v2f32 (FMAXNMv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm)))>;
5601+
def : Pat<(v4f16 (fmaxnum_ieee (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
5602+
(v4f16 (FMAXNMv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm)))>;
5603+
55665604
// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
55675605
// instruction expects the addend first, while the fma intrinsic puts it last.
55685606
defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla",

‎llvm/test/CodeGen/AArch64/combine_andor_with_cmps.ll

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -31,18 +31,15 @@ define i1 @test2(double %arg1, double %arg2, double %arg3) #0 {
3131
ret i1 %or1
3232
}
3333

34-
; It is illegal to apply the optimization in the following two test cases
35-
; because FMINNUM_IEEE and FMAXNUM_IEEE are not supported.
36-
3734
define i1 @test3(float %arg1, float %arg2, float %arg3) {
3835
; CHECK-LABEL: test3:
3936
; CHECK: // %bb.0:
4037
; CHECK-NEXT: fmov s3, #1.00000000
4138
; CHECK-NEXT: fadd s0, s0, s3
4239
; CHECK-NEXT: fmov s3, #2.00000000
4340
; CHECK-NEXT: fadd s1, s1, s3
44-
; CHECK-NEXT: fcmp s1, s2
45-
; CHECK-NEXT: fccmp s0, s2, #0, lt
41+
; CHECK-NEXT: fmaxnm s0, s0, s1
42+
; CHECK-NEXT: fcmp s0, s2
4643
; CHECK-NEXT: cset w0, lt
4744
; CHECK-NEXT: ret
4845
%add1 = fadd nnan float %arg1, 1.0
@@ -60,8 +57,8 @@ define i1 @test4(float %arg1, float %arg2, float %arg3) {
6057
; CHECK-NEXT: fadd s0, s0, s3
6158
; CHECK-NEXT: fmov s3, #2.00000000
6259
; CHECK-NEXT: fadd s1, s1, s3
63-
; CHECK-NEXT: fcmp s1, s2
64-
; CHECK-NEXT: fccmp s0, s2, #4, gt
60+
; CHECK-NEXT: fminnm s0, s0, s1
61+
; CHECK-NEXT: fcmp s0, s2
6562
; CHECK-NEXT: cset w0, gt
6663
; CHECK-NEXT: ret
6764
%add1 = fadd nnan float %arg1, 1.0

‎llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc --mtriple=aarch64 --mattr=+fullfp16 < %s | FileCheck %s --check-prefix=AARCH64
3+
4+
define <2 x double> @max_v2f64(<2 x double> %a, <2 x double> %b) {
5+
; AARCH64-LABEL: max_v2f64:
6+
; AARCH64: // %bb.0: // %entry
7+
; AARCH64-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
8+
; AARCH64-NEXT: ret
9+
entry:
10+
%c = call nnan <2 x double> @llvm.maximumnum.v2f64(<2 x double> %a, <2 x double> %b)
11+
ret <2 x double> %c
12+
}
13+
14+
define <4 x float> @max_v4f32(<4 x float> %a, <4 x float> %b) {
15+
; AARCH64-LABEL: max_v4f32:
16+
; AARCH64: // %bb.0: // %entry
17+
; AARCH64-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
18+
; AARCH64-NEXT: ret
19+
entry:
20+
%c = call nnan <4 x float> @llvm.maximumnum.v2f64(<4 x float> %a, <4 x float> %b)
21+
ret <4 x float> %c
22+
}
23+
24+
25+
define <8 x half> @max_v8f16(<8 x half> %a, <8 x half> %b) {
26+
; AARCH64-LABEL: max_v8f16:
27+
; AARCH64: // %bb.0: // %entry
28+
; AARCH64-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
29+
; AARCH64-NEXT: ret
30+
entry:
31+
%c = call nnan <8 x half> @llvm.maximumnum.v4f16(<8 x half> %a, <8 x half> %b)
32+
ret <8 x half> %c
33+
}
34+
35+
define <1 x double> @max_v1f64(<1 x double> %a, <1 x double> %b) {
36+
; AARCH64-LABEL: max_v1f64:
37+
; AARCH64: // %bb.0: // %entry
38+
; AARCH64-NEXT: fmaxnm d0, d0, d1
39+
; AARCH64-NEXT: ret
40+
entry:
41+
%c = call nnan <1 x double> @llvm.maximumnum.v1f64(<1 x double> %a, <1 x double> %b)
42+
ret <1 x double> %c
43+
}
44+
45+
define double @max_f64(double %a, double %b) {
46+
; AARCH64-LABEL: max_f64:
47+
; AARCH64: // %bb.0: // %entry
48+
; AARCH64-NEXT: fmaxnm d0, d0, d1
49+
; AARCH64-NEXT: ret
50+
entry:
51+
%c = call nnan double @llvm.maximumnum.f64(double %a, double %b)
52+
ret double %c
53+
}
54+
55+
define float @max_f32(float %a, float %b) {
56+
; AARCH64-LABEL: max_f32:
57+
; AARCH64: // %bb.0: // %entry
58+
; AARCH64-NEXT: fmaxnm s0, s0, s1
59+
; AARCH64-NEXT: ret
60+
entry:
61+
%c = call nnan float @llvm.maximumnum.f32(float %a, float %b)
62+
ret float %c
63+
}
64+
65+
define half @max_f16(half %a, half %b) {
66+
; AARCH64-LABEL: max_f16:
67+
; AARCH64: // %bb.0: // %entry
68+
; AARCH64-NEXT: fmaxnm h0, h0, h1
69+
; AARCH64-NEXT: ret
70+
entry:
71+
%c = call nnan half @llvm.maximumnum.f16(half %a, half %b)
72+
ret half %c
73+
}
74+
75+
define <2 x double> @min_v2f64(<2 x double> %a, <2 x double> %b) {
76+
; AARCH64-LABEL: min_v2f64:
77+
; AARCH64: // %bb.0: // %entry
78+
; AARCH64-NEXT: fminnm v0.2d, v0.2d, v1.2d
79+
; AARCH64-NEXT: ret
80+
entry:
81+
%c = call nnan <2 x double> @llvm.minimumnum.v2f64(<2 x double> %a, <2 x double> %b)
82+
ret <2 x double> %c
83+
}
84+
85+
define <4 x float> @min_v4f32(<4 x float> %a, <4 x float> %b) {
86+
; AARCH64-LABEL: min_v4f32:
87+
; AARCH64: // %bb.0: // %entry
88+
; AARCH64-NEXT: fminnm v0.4s, v0.4s, v1.4s
89+
; AARCH64-NEXT: ret
90+
entry:
91+
%c = call nnan <4 x float> @llvm.minimumnum.v2f64(<4 x float> %a, <4 x float> %b)
92+
ret <4 x float> %c
93+
}
94+
95+
96+
define <8 x half> @min_v8f16(<8 x half> %a, <8 x half> %b) {
97+
; AARCH64-LABEL: min_v8f16:
98+
; AARCH64: // %bb.0: // %entry
99+
; AARCH64-NEXT: fminnm v0.8h, v0.8h, v1.8h
100+
; AARCH64-NEXT: ret
101+
entry:
102+
%c = call nnan <8 x half> @llvm.minimumnum.v4f16(<8 x half> %a, <8 x half> %b)
103+
ret <8 x half> %c
104+
}
105+
106+
define <1 x double> @min_v1f64(<1 x double> %a, <1 x double> %b) {
107+
; AARCH64-LABEL: min_v1f64:
108+
; AARCH64: // %bb.0: // %entry
109+
; AARCH64-NEXT: fminnm d0, d0, d1
110+
; AARCH64-NEXT: ret
111+
entry:
112+
%c = call nnan <1 x double> @llvm.minimumnum.v1f64(<1 x double> %a, <1 x double> %b)
113+
ret <1 x double> %c
114+
}
115+
116+
define double @min_f64(double %a, double %b) {
117+
; AARCH64-LABEL: min_f64:
118+
; AARCH64: // %bb.0: // %entry
119+
; AARCH64-NEXT: fminnm d0, d0, d1
120+
; AARCH64-NEXT: ret
121+
entry:
122+
%c = call nnan double @llvm.minimumnum.f64(double %a, double %b)
123+
ret double %c
124+
}
125+
126+
define float @min_f32(float %a, float %b) {
127+
; AARCH64-LABEL: min_f32:
128+
; AARCH64: // %bb.0: // %entry
129+
; AARCH64-NEXT: fminnm s0, s0, s1
130+
; AARCH64-NEXT: ret
131+
entry:
132+
%c = call nnan float @llvm.minimumnum.f32(float %a, float %b)
133+
ret float %c
134+
}
135+
136+
define half @min_f16(half %a, half %b) {
137+
; AARCH64-LABEL: min_f16:
138+
; AARCH64: // %bb.0: // %entry
139+
; AARCH64-NEXT: fminnm h0, h0, h1
140+
; AARCH64-NEXT: ret
141+
entry:
142+
%c = call nnan half @llvm.minimumnum.f16(half %a, half %b)
143+
ret half %c
144+
}
145+

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