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address comment, add gfx12 asm/dasm test
1 parent 94d2d36 commit 85d1675

17 files changed

+491
-236
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1255,7 +1255,7 @@ def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
12551255

12561256
class FPT16VCSrcInputMods<bit IsFake16 = 1>
12571257
: FPInputMods<FP16VCSrcInputModsMatchClass<IsFake16>> {
1258-
let EncoderMethod = "getMachineOpValueT16";
1258+
let EncoderMethod = "getMachineOpValueT16";
12591259
}
12601260
def FP32VCSrcInputMods : FPInputMods<FP32VCSrcInputModsMatchClass>;
12611261

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,10 +1155,10 @@ multiclass f16_fp_Pats<Instruction cvt_f16_f32_inst_e64, Instruction cvt_f32_f16
11551155
>;
11561156
}
11571157

1158-
let SubtargetPredicate = NotHasTrue16BitInsts in
1158+
let True16Predicate = NotHasTrue16BitInsts in
11591159
defm : f16_fp_Pats<V_CVT_F16_F32_e64, V_CVT_F32_F16_e64>;
11601160

1161-
let SubtargetPredicate = UseFakeTrue16Insts in
1161+
let True16Predicate = UseFakeTrue16Insts in
11621162
defm : f16_fp_Pats<V_CVT_F16_F32_fake16_e64, V_CVT_F32_F16_fake16_e64>;
11631163

11641164
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,7 @@ defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_
295295
defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_sint>;
296296
let FPDPRounding = 1, isReMaterializable = 0 in {
297297
// V_CVT_F16_F32 and V_CVT_F32_F16 are special cases because they are
298-
// present in targets without Has16BitInsts. Otherwise they can use
298+
// present in targets without Has16BitInsts. Otherwise they could use
299299
// class VOP1Inst_t16
300300
let OtherPredicates = [NotHasTrue16BitInsts] in
301301
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, any_fpround>;

‎llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-fake16.mir

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,13 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
22
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
3-
# XFAIL: *
4-
# FIXME-TRUE16. reenable after CVT_F16_U16_fake16 is supported in MC
53

64
---
75
name: cvt_hi_f32_f16
86
body: |
97
bb.0:
108
; GCN-LABEL: name: cvt_hi_f32_f16
119
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
12-
; GCN-NEXT: [[V_CVT_F16_U16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
10+
; GCN-NEXT: [[V_CVT_F16_U16_t16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_t16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
1311
; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
1412
; GCN-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, [[V_CVT_F16_U16_e64_]], implicit $exec
1513
; GCN-NEXT: [[V_CVT_F32_F16_t16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_t16_e64 0, [[V_LSHRREV_B32_e64_]], 0, 0, implicit $mode, implicit $exec

‎llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
22
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
33
# XFAIL: *
4-
# FIXME-TRUE16. reenable after CVT_F16_U16_t16 is supported in MC
4+
# FIXME-TRUE16. reenable after CVT_F16_U16_t16 is supported in CodeGen
55

66
---
77
name: cvt_hi_f32_f16

‎llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s

Lines changed: 40 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -351,48 +351,54 @@ v_cvt_f32_bf8 v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc
351351
v_cvt_f32_bf8 v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe
352352
// GFX12: encoding: [0xfa,0xda,0x02,0x7e,0x03,0x1b,0x00,0x2e]
353353

354-
v_cvt_f16_f32 v5, v1 quad_perm:[3,2,1,0]
354+
v_cvt_f16_f32 v5.l, v1 quad_perm:[3,2,1,0]
355355
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0xff]
356356

357-
v_cvt_f16_f32 v5, v1 quad_perm:[0,1,2,3]
357+
v_cvt_f16_f32 v5.l, v1 quad_perm:[0,1,2,3]
358358
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xff]
359359

360-
v_cvt_f16_f32 v5, v1 row_mirror
360+
v_cvt_f16_f32 v5.l, v1 row_mirror
361361
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0xff]
362362

363-
v_cvt_f16_f32 v5, v1 row_half_mirror
363+
v_cvt_f16_f32 v5.l, v1 row_half_mirror
364364
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0xff]
365365

366-
v_cvt_f16_f32 v5, v1 row_shl:1
366+
v_cvt_f16_f32 v5.l, v1 row_shl:1
367367
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0xff]
368368

369-
v_cvt_f16_f32 v5, v1 row_shl:15
369+
v_cvt_f16_f32 v5.l, v1 row_shl:15
370370
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0xff]
371371

372-
v_cvt_f16_f32 v5, v1 row_shr:1
372+
v_cvt_f16_f32 v5.l, v1 row_shr:1
373373
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0xff]
374374

375-
v_cvt_f16_f32 v5, v1 row_shr:15
375+
v_cvt_f16_f32 v5.l, v1 row_shr:15
376376
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0xff]
377377

378-
v_cvt_f16_f32 v5, v1 row_ror:1
378+
v_cvt_f16_f32 v5.l, v1 row_ror:1
379379
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0xff]
380380

381-
v_cvt_f16_f32 v5, v1 row_ror:15
381+
v_cvt_f16_f32 v5.l, v1 row_ror:15
382382
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0xff]
383383

384-
v_cvt_f16_f32 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
384+
v_cvt_f16_f32 v5.l, v1 row_share:0 row_mask:0xf bank_mask:0xf
385385
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x50,0x01,0xff]
386386

387-
v_cvt_f16_f32 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
387+
v_cvt_f16_f32 v5.l, v1 row_share:15 row_mask:0x0 bank_mask:0x1
388388
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x01]
389389

390-
v_cvt_f16_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
390+
v_cvt_f16_f32 v5.l, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
391391
// GFX12: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x60,0x09,0x13]
392392

393-
v_cvt_f16_f32 v127, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
393+
v_cvt_f16_f32 v127.l, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
394394
// GFX12: encoding: [0xfa,0x14,0xfe,0x7e,0xff,0x6f,0x35,0x30]
395395

396+
v_cvt_f16_f32 v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
397+
// GFX12: encoding: [0xfa,0x14,0x0a,0x7f,0x01,0x60,0x09,0x13]
398+
399+
v_cvt_f16_f32 v127.h, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
400+
// GFX12: encoding: [0xfa,0x14,0xfe,0x7f,0xff,0x6f,0x35,0x30]
401+
396402
v_cvt_f16_i16 v5, v1 quad_perm:[3,2,1,0]
397403
// GFX12: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
398404

@@ -477,48 +483,54 @@ v_cvt_f16_u16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
477483
v_cvt_f16_u16 v127, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
478484
// GFX12: encoding: [0xfa,0xa0,0xfe,0x7e,0x7f,0x6f,0x05,0x30]
479485

480-
v_cvt_f32_f16 v5, v1 quad_perm:[3,2,1,0]
486+
v_cvt_f32_f16 v5, v1.l quad_perm:[3,2,1,0]
481487
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0xff]
482488

483-
v_cvt_f32_f16 v5, v1 quad_perm:[0,1,2,3]
489+
v_cvt_f32_f16 v5, v1.l quad_perm:[0,1,2,3]
484490
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xff]
485491

486-
v_cvt_f32_f16 v5, v1 row_mirror
492+
v_cvt_f32_f16 v5, v1.l row_mirror
487493
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0xff]
488494

489-
v_cvt_f32_f16 v5, v1 row_half_mirror
495+
v_cvt_f32_f16 v5, v1.l row_half_mirror
490496
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0xff]
491497

492-
v_cvt_f32_f16 v5, v1 row_shl:1
498+
v_cvt_f32_f16 v5, v1.l row_shl:1
493499
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0xff]
494500

495-
v_cvt_f32_f16 v5, v1 row_shl:15
501+
v_cvt_f32_f16 v5, v1.l row_shl:15
496502
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0xff]
497503

498-
v_cvt_f32_f16 v5, v1 row_shr:1
504+
v_cvt_f32_f16 v5, v1.l row_shr:1
499505
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0xff]
500506

501-
v_cvt_f32_f16 v5, v1 row_shr:15
507+
v_cvt_f32_f16 v5, v1.l row_shr:15
502508
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0xff]
503509

504-
v_cvt_f32_f16 v5, v1 row_ror:1
510+
v_cvt_f32_f16 v5, v1.l row_ror:1
505511
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0xff]
506512

507-
v_cvt_f32_f16 v5, v1 row_ror:15
513+
v_cvt_f32_f16 v5, v1.l row_ror:15
508514
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0xff]
509515

510-
v_cvt_f32_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
516+
v_cvt_f32_f16 v5, v1.l row_share:0 row_mask:0xf bank_mask:0xf
511517
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x50,0x01,0xff]
512518

513-
v_cvt_f32_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
519+
v_cvt_f32_f16 v5, v1.l row_share:15 row_mask:0x0 bank_mask:0x1
514520
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x5f,0x01,0x01]
515521

516-
v_cvt_f32_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
522+
v_cvt_f32_f16 v5, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
517523
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x60,0x09,0x13]
518524

519-
v_cvt_f32_f16 v255, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
525+
v_cvt_f32_f16 v255, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
520526
// GFX12: encoding: [0xfa,0x16,0xfe,0x7f,0x7f,0x6f,0x35,0x30]
521527

528+
v_cvt_f32_f16 v5, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
529+
// GFX12: encoding: [0xfa,0x16,0x0a,0x7e,0x81,0x60,0x09,0x13]
530+
531+
v_cvt_f32_f16 v255, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
532+
// GFX12: encoding: [0xfa,0x16,0xfe,0x7f,0xff,0x6f,0x35,0x30]
533+
522534
v_cvt_f32_i32 v5, v1 quad_perm:[3,2,1,0]
523535
// GFX12: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0xff]
524536

‎llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -87,15 +87,21 @@ v_cvt_f32_bf8 v5, v1 dpp8:[0,1,2,3,4,5,6,7]
8787
v_cvt_f32_bf8 v1, v3 dpp8:[7,6,5,4,3,2,1,0]
8888
// GFX12: encoding: [0xe9,0xda,0x02,0x7e,0x03,0x77,0x39,0x05]
8989

90-
v_cvt_f16_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
90+
v_cvt_f16_f32 v5.l, v1 dpp8:[7,6,5,4,3,2,1,0]
9191
// GFX12: encoding: [0xe9,0x14,0x0a,0x7e,0x01,0x77,0x39,0x05]
9292

93-
v_cvt_f16_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
93+
v_cvt_f16_f32 v5.l, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
9494
// GFX12: encoding: [0xea,0x14,0x0a,0x7e,0x01,0x77,0x39,0x05]
9595

96-
v_cvt_f16_f32 v127, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
96+
v_cvt_f16_f32 v127.l, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
9797
// GFX12: encoding: [0xe9,0x14,0xfe,0x7e,0xff,0x00,0x00,0x00]
9898

99+
v_cvt_f16_f32 v5.h, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
100+
// GFX12: encoding: [0xea,0x14,0x0a,0x7f,0x01,0x77,0x39,0x05]
101+
102+
v_cvt_f16_f32 v127.h, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
103+
// GFX12: encoding: [0xe9,0x14,0xfe,0x7f,0xff,0x00,0x00,0x00]
104+
99105
v_cvt_f16_i16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
100106
// GFX12: encoding: [0xe9,0xa2,0x0a,0x7e,0x01,0x77,0x39,0x05]
101107

@@ -114,15 +120,21 @@ v_cvt_f16_u16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
114120
v_cvt_f16_u16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
115121
// GFX12: encoding: [0xe9,0xa0,0xfe,0x7e,0x7f,0x00,0x00,0x00]
116122

117-
v_cvt_f32_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
123+
v_cvt_f32_f16 v5, v1.l dpp8:[7,6,5,4,3,2,1,0]
118124
// GFX12: encoding: [0xe9,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05]
119125

120-
v_cvt_f32_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
126+
v_cvt_f32_f16 v5, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1
121127
// GFX12: encoding: [0xea,0x16,0x0a,0x7e,0x01,0x77,0x39,0x05]
122128

123-
v_cvt_f32_f16 v255, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
129+
v_cvt_f32_f16 v255, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:0
124130
// GFX12: encoding: [0xe9,0x16,0xfe,0x7f,0x7f,0x00,0x00,0x00]
125131

132+
v_cvt_f32_f16 v5, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1
133+
// GFX12: encoding: [0xea,0x16,0x0a,0x7e,0x81,0x77,0x39,0x05]
134+
135+
v_cvt_f32_f16 v255, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
136+
// GFX12: encoding: [0xe9,0x16,0xfe,0x7f,0xff,0x00,0x00,0x00]
137+
126138
v_cvt_f32_i32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
127139
// GFX12: encoding: [0xe9,0x0a,0x0a,0x7e,0x01,0x77,0x39,0x05]
128140

‎llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s

Lines changed: 52 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -18,14 +18,14 @@ v_cos_f16_e32 v255, v1
1818
v_cos_f16_e32 v5, v199
1919
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
2020

21-
v_cvt_f16_f32_e32 v128, 0xaf123456
22-
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
21+
v_cvt_f16_f32_e32 v128.l, 0xaf123456
22+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
2323

24-
v_cvt_f16_f32_e32 v255, v1
25-
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
24+
v_cvt_f16_f32_e32 v255.l, v1
25+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
2626

27-
v_cvt_f16_f32_e32 v255, v255
28-
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
27+
v_cvt_f16_f32_e32 v255.l, v255
28+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
2929

3030
v_cvt_f16_i16_e32 v128, 0xfe0b
3131
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -45,8 +45,8 @@ v_cvt_f16_u16_e32 v255, v1
4545
v_cvt_f16_u16_e32 v5, v199
4646
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
4747

48-
v_cvt_f32_f16_e32 v5, v199
49-
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
48+
v_cvt_f32_f16_e32 v5, v199.l
49+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
5050

5151
v_cvt_i16_f16_e32 v128, 0xfe0b
5252
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
@@ -237,13 +237,13 @@ v_cos_f16_e32 v255, v1 quad_perm:[3,2,1,0]
237237
v_cos_f16_e32 v5, v199 quad_perm:[3,2,1,0]
238238
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
239239

240-
v_cvt_f16_f32_e32 v128, 0xaf123456 quad_perm:[3,2,1,0]
240+
v_cvt_f16_f32_e32 v128.l, 0xaf123456 quad_perm:[3,2,1,0]
241241
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
242242

243-
v_cvt_f16_f32_e32 v255, v1 quad_perm:[3,2,1,0]
243+
v_cvt_f16_f32_e32 v255.l, v1 quad_perm:[3,2,1,0]
244244
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
245245

246-
v_cvt_f16_f32_e32 v255, v255 quad_perm:[3,2,1,0]
246+
v_cvt_f16_f32_e32 v255.l, v255 quad_perm:[3,2,1,0]
247247
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
248248

249249
v_cvt_f16_i16_e32 v255, v1 quad_perm:[3,2,1,0]
@@ -258,7 +258,7 @@ v_cvt_f16_u16_e32 v255, v1 quad_perm:[3,2,1,0]
258258
v_cvt_f16_u16_e32 v5, v199 quad_perm:[3,2,1,0]
259259
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
260260

261-
v_cvt_f32_f16_e32 v5, v199 quad_perm:[3,2,1,0]
261+
v_cvt_f32_f16_e32 v5, v199.l quad_perm:[3,2,1,0]
262262
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
263263

264264
v_cvt_i16_f16_e32 v255, v1 quad_perm:[3,2,1,0]
@@ -384,13 +384,13 @@ v_cos_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
384384
v_cos_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
385385
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
386386

387-
v_cvt_f16_f32_e32 v128, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
387+
v_cvt_f16_f32_e32 v128.l, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
388388
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
389389

390-
v_cvt_f16_f32_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
390+
v_cvt_f16_f32_e32 v255.l, v1 dpp8:[7,6,5,4,3,2,1,0]
391391
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
392392

393-
v_cvt_f16_f32_e32 v255, v255 dpp8:[7,6,5,4,3,2,1,0]
393+
v_cvt_f16_f32_e32 v255.l, v255 dpp8:[7,6,5,4,3,2,1,0]
394394
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
395395

396396
v_cvt_f16_i16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
@@ -405,7 +405,7 @@ v_cvt_f16_u16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
405405
v_cvt_f16_u16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
406406
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
407407

408-
v_cvt_f32_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
408+
v_cvt_f32_f16_e32 v5, v199.l dpp8:[7,6,5,4,3,2,1,0]
409409
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
410410

411411
v_cvt_i16_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
@@ -518,3 +518,39 @@ v_trunc_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
518518

519519
v_trunc_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
520520
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
521+
522+
v_cvt_f32_f16_e32 v5, v199.h
523+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
524+
525+
v_cvt_f32_f16_e32 v5, v199.h quad_perm:[3,2,1,0]
526+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
527+
528+
v_cvt_f32_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
529+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
530+
531+
v_cvt_f16_f32_e32 v128.h, 0xaf123456
532+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
533+
534+
v_cvt_f16_f32_e32 v255.h, v1
535+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
536+
537+
v_cvt_f16_f32_e32 v255.h, v255
538+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
539+
540+
v_cvt_f16_f32_e32 v128.h, 0xaf123456 quad_perm:[3,2,1,0]
541+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
542+
543+
v_cvt_f16_f32_e32 v255.h, v1 quad_perm:[3,2,1,0]
544+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
545+
546+
v_cvt_f16_f32_e32 v255.h, v255 quad_perm:[3,2,1,0]
547+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
548+
549+
v_cvt_f16_f32_e32 v128.h, 0xaf123456 dpp8:[7,6,5,4,3,2,1,0]
550+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
551+
552+
v_cvt_f16_f32_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
553+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
554+
555+
v_cvt_f16_f32_e32 v255.h, v255.h dpp8:[7,6,5,4,3,2,1,0]
556+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

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