@@ -120,15 +120,17 @@ class MxSet<int eew> {
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!eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
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}
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- class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist> {
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+ class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist,
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+ list<LMULInfo> mxlistfw> {
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RegisterClass fprclass = regclass;
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string FX = fx;
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list<LMULInfo> MxList = mxlist;
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+ list<LMULInfo> MxListFW = mxlistfw;
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}
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- def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet<16>.m>;
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- def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet<32>.m>;
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- def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m>;
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+ def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet<16>.m, [V_MF4, V_MF2, V_M1, V_M2, V_M4] >;
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+ def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet<32>.m, [V_MF2, V_M1, V_M2, V_M4] >;
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+ def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m, [] >;
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defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
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@@ -2012,7 +2014,7 @@ multiclass VPseudoBinaryW_VX_LMUL<LMULInfo m> {
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multiclass VPseudoBinaryW_VF {
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foreach f = FPListW in
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- foreach m = f.MxList in
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+ foreach m = f.MxListFW in
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defm "_V" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass,
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f.fprclass, m,
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"@earlyclobber $rd">;
@@ -2040,7 +2042,7 @@ multiclass VPseudoBinaryW_WX_LMUL<LMULInfo m> {
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multiclass VPseudoBinaryW_WF {
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foreach f = FPListW in
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- foreach m = f.MxList in
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+ foreach m = f.MxListFW in
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defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
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f.fprclass, m>;
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}
@@ -2868,7 +2870,7 @@ multiclass VPseudoTernaryW_VX<LMULInfo m> {
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multiclass VPseudoTernaryW_VF {
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defvar constraint = "@earlyclobber $rd";
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foreach f = FPListW in
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- foreach m = f.MxList in
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+ foreach m = f.MxListFW in
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defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
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m.vrclass, m, constraint>;
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}
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