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Use & instead of sub to adjust shift
Signed-off-by: John Lu <[email protected]>
1 parent 5a0b7f5 commit 862c784

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2 files changed

+128
-281
lines changed

2 files changed

+128
-281
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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4047,16 +4047,16 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
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SelectionDAG &DAG = DCI.DAG;
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40494049
if (!CRHS) {
4050-
// shl i64 X, Y -> [0, shl i32 X, (Y - 32)]
4050+
// shl i64 X, Y -> [0, shl i32 X, (Y & 0x1F)]
40514051
if (VT == MVT::i64) {
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KnownBits Known = DAG.computeKnownBits(RHS);
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if (Known.getMinValue().getZExtValue() >= 32) {
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SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, RHS);
4055-
const SDValue C32 = DAG.getConstant(32, SL, MVT::i32);
4056-
SDValue ShiftAmt =
4057-
DAG.getNode(ISD::SUB, SL, MVT::i32, truncShiftAmt, C32);
4055+
const SDValue C31 = DAG.getConstant(31, SL, MVT::i32);
4056+
SDValue MaskedShiftAmt =
4057+
DAG.getNode(ISD::AND, SL, MVT::i32, truncShiftAmt, C31);
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SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
4059-
SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
4059+
SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, MaskedShiftAmt);
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const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
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SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
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return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);

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