optimize check and fix conflict in test

Author: Fros1er

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -27004,7 +27004,7 @@ static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
       Src0.getValueType().getVectorElementType() != EltVT ||
       Src1.getValueType().getVectorElementType() != EltVT ||
       !(IsBothSplatVector || TLI.isExtractVecEltCheap(VT, Index0)) ||
-      (LegalTypes && !TLI.isOperationLegalOrCustom(Opcode, EltVT)) ||
+      (LegalTypes && !TLI.isTypeLegal(EltVT)) ||
       !(EltAction == TargetLoweringBase::Legal ||
         EltAction == TargetLoweringBase::Custom))
     return SDValue();

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32NOM
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM
 
-; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32M
 ; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M
 
 define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
@@ -864,13 +864,44 @@ define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
 }
 
 define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
+; RV32NOM-LABEL: vmul_xx_nxv8i64:
+; RV32NOM:       # %bb.0:
+; RV32NOM-NEXT:    addi sp, sp, -16
+; RV32NOM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32NOM-NEXT:    call __muldi3
+; RV32NOM-NEXT:    sw a1, 4(sp)
+; RV32NOM-NEXT:    sw a0, 0(sp)
+; RV32NOM-NEXT:    mv a0, sp
+; RV32NOM-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; RV32NOM-NEXT:    vlse64.v v8, (a0), zero
+; RV32NOM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32NOM-NEXT:    addi sp, sp, 16
+; RV32NOM-NEXT:    ret
+;
 ; RV64NOM-LABEL: vmul_xx_nxv8i64:
 ; RV64NOM:       # %bb.0:
 ; RV64NOM-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
 ; RV64NOM-NEXT:    vmv.v.x v8, a0
 ; RV64NOM-NEXT:    vmul.vx v8, v8, a1
 ; RV64NOM-NEXT:    ret
 ;
+; RV32M-LABEL: vmul_xx_nxv8i64:
+; RV32M:       # %bb.0:
+; RV32M-NEXT:    addi sp, sp, -16
+; RV32M-NEXT:    mul a4, a0, a2
+; RV32M-NEXT:    sw a4, 8(sp)
+; RV32M-NEXT:    mul a3, a0, a3
+; RV32M-NEXT:    mulhu a0, a0, a2
+; RV32M-NEXT:    add a0, a0, a3
+; RV32M-NEXT:    mul a1, a1, a2
+; RV32M-NEXT:    add a0, a0, a1
+; RV32M-NEXT:    sw a0, 12(sp)
+; RV32M-NEXT:    addi a0, sp, 8
+; RV32M-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
+; RV32M-NEXT:    vlse64.v v8, (a0), zero
+; RV32M-NEXT:    addi sp, sp, 16
+; RV32M-NEXT:    ret
+;
 ; RV64M-LABEL: vmul_xx_nxv8i64:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    mul a0, a0, a1