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[RISCV][GISel] Add initial pre-legalizer combiners copying from AArch64.
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9 files changed

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‎llvm/lib/Target/RISCV/CMakeLists.txt

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@@ -17,6 +17,10 @@ tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
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set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
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tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
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tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="RISCVO0PreLegalizerCombiner")
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tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="RISCVPreLegalizerCombiner")
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add_public_tablegen_target(RISCVCommonTableGen)
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@@ -49,6 +53,8 @@ add_llvm_target(RISCVCodeGen
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GISel/RISCVCallLowering.cpp
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GISel/RISCVInstructionSelector.cpp
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GISel/RISCVLegalizerInfo.cpp
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GISel/RISCVO0PreLegalizerCombiner.cpp
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GISel/RISCVPreLegalizerCombiner.cpp
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GISel/RISCVRegisterBankInfo.cpp
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LINK_COMPONENTS

‎llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp

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//=== RISCVO0PreLegalizerCombiner.cpp -------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#define GET_GICOMBINER_DEPS
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#include "RISCVGenO0PreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_DEPS
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#define DEBUG_TYPE "riscv-O0-prelegalizer-combiner"
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using namespace llvm;
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namespace {
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#define GET_GICOMBINER_TYPES
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#include "RISCVGenO0PreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_TYPES
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class RISCVO0PreLegalizerCombinerImpl : public Combiner {
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protected:
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// TODO: Make CombinerHelper methods const.
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mutable CombinerHelper Helper;
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const RISCVO0PreLegalizerCombinerImplRuleConfig &RuleConfig;
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const RISCVSubtarget &STI;
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public:
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RISCVO0PreLegalizerCombinerImpl(
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MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
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GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
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const RISCVO0PreLegalizerCombinerImplRuleConfig &RuleConfig,
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const RISCVSubtarget &STI);
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static const char *getName() { return "RISCVO0PreLegalizerCombiner"; }
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bool tryCombineAll(MachineInstr &I) const override;
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private:
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#define GET_GICOMBINER_CLASS_MEMBERS
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#include "RISCVGenO0PreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_CLASS_MEMBERS
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};
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#define GET_GICOMBINER_IMPL
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#include "RISCVGenO0PreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_IMPL
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RISCVO0PreLegalizerCombinerImpl::RISCVO0PreLegalizerCombinerImpl(
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MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
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GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
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const RISCVO0PreLegalizerCombinerImplRuleConfig &RuleConfig,
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const RISCVSubtarget &STI)
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: Combiner(MF, CInfo, TPC, &KB, CSEInfo),
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Helper(Observer, B, /*IsPreLegalize*/ true, &KB), RuleConfig(RuleConfig),
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STI(STI),
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#define GET_GICOMBINER_CONSTRUCTOR_INITS
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#include "RISCVGenO0PreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_CONSTRUCTOR_INITS
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{
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}
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// Pass boilerplate
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// ================
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class RISCVO0PreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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RISCVO0PreLegalizerCombiner();
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StringRef getPassName() const override {
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return "RISCVO0PreLegalizerCombiner";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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RISCVO0PreLegalizerCombinerImplRuleConfig RuleConfig;
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};
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} // end anonymous namespace
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void RISCVO0PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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RISCVO0PreLegalizerCombiner::RISCVO0PreLegalizerCombiner()
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: MachineFunctionPass(ID) {
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initializeRISCVO0PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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if (!RuleConfig.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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bool RISCVO0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto &TPC = getAnalysis<TargetPassConfig>();
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const Function &F = MF.getFunction();
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GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, /*EnableOpt*/ false,
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F.hasOptSize(), F.hasMinSize());
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RISCVO0PreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *KB,
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/*CSEInfo*/ nullptr, RuleConfig, ST);
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return Impl.combineMachineInstrs();
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}
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char RISCVO0PreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(RISCVO0PreLegalizerCombiner, DEBUG_TYPE,
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"Combine RISCV machine instrs before legalization", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
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INITIALIZE_PASS_END(RISCVO0PreLegalizerCombiner, DEBUG_TYPE,
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"Combine RISCV machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createRISCVO0PreLegalizerCombiner() {
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return new RISCVO0PreLegalizerCombiner();
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}
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} // end namespace llvm

‎llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp

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//=== RISCVPreLegalizerCombiner.cpp ---------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#define GET_GICOMBINER_DEPS
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#include "RISCVGenPreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_DEPS
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#define DEBUG_TYPE "riscv-prelegalizer-combiner"
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using namespace llvm;
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namespace {
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#define GET_GICOMBINER_TYPES
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#include "RISCVGenPreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_TYPES
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class RISCVPreLegalizerCombinerImpl : public Combiner {
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protected:
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// TODO: Make CombinerHelper methods const.
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mutable CombinerHelper Helper;
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const RISCVPreLegalizerCombinerImplRuleConfig &RuleConfig;
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const RISCVSubtarget &STI;
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public:
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RISCVPreLegalizerCombinerImpl(
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MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
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GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
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const RISCVPreLegalizerCombinerImplRuleConfig &RuleConfig,
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const RISCVSubtarget &STI, MachineDominatorTree *MDT,
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const LegalizerInfo *LI);
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static const char *getName() { return "RISCV00PreLegalizerCombiner"; }
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bool tryCombineAll(MachineInstr &I) const override;
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private:
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#define GET_GICOMBINER_CLASS_MEMBERS
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#include "RISCVGenPreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_CLASS_MEMBERS
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};
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#define GET_GICOMBINER_IMPL
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#include "RISCVGenPreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_IMPL
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RISCVPreLegalizerCombinerImpl::RISCVPreLegalizerCombinerImpl(
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MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
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GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
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const RISCVPreLegalizerCombinerImplRuleConfig &RuleConfig,
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const RISCVSubtarget &STI, MachineDominatorTree *MDT,
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const LegalizerInfo *LI)
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: Combiner(MF, CInfo, TPC, &KB, CSEInfo),
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Helper(Observer, B, /*IsPreLegalize*/ true, &KB, MDT, LI),
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RuleConfig(RuleConfig), STI(STI),
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#define GET_GICOMBINER_CONSTRUCTOR_INITS
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#include "RISCVGenPreLegalizeGICombiner.inc"
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#undef GET_GICOMBINER_CONSTRUCTOR_INITS
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{
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}
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// Pass boilerplate
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// ================
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class RISCVPreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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RISCVPreLegalizerCombiner();
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StringRef getPassName() const override { return "RISCVPreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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RISCVPreLegalizerCombinerImplRuleConfig RuleConfig;
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};
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} // end anonymous namespace
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void RISCVPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<GISelCSEAnalysisWrapperPass>();
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AU.addPreserved<GISelCSEAnalysisWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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RISCVPreLegalizerCombiner::RISCVPreLegalizerCombiner()
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: MachineFunctionPass(ID) {
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initializeRISCVPreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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if (!RuleConfig.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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bool RISCVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto &TPC = getAnalysis<TargetPassConfig>();
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// Enable CSE.
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GISelCSEAnalysisWrapper &Wrapper =
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getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
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auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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const auto *LI = ST.getLegalizerInfo();
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const Function &F = MF.getFunction();
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bool EnableOpt =
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MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
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GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
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CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
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F.hasMinSize());
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RISCVPreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *KB, CSEInfo, RuleConfig,
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ST, MDT, LI);
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return Impl.combineMachineInstrs();
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}
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char RISCVPreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(RISCVPreLegalizerCombiner, DEBUG_TYPE,
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"Combine RISCV machine instrs before legalization", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
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INITIALIZE_PASS_END(RISCVPreLegalizerCombiner, DEBUG_TYPE,
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"Combine RISCV machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createRISCVPreLegalizerCombiner() {
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return new RISCVPreLegalizerCombiner();
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}
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} // end namespace llvm

‎llvm/lib/Target/RISCV/RISCV.h

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@@ -80,6 +80,12 @@ InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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RISCVSubtarget &,
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RISCVRegisterBankInfo &);
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void initializeRISCVDAGToDAGISelPass(PassRegistry &);
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FunctionPass *createRISCVO0PreLegalizerCombiner();
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void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createRISCVPreLegalizerCombiner();
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void initializeRISCVPreLegalizerCombinerPass(PassRegistry &);
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} // namespace llvm
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#endif

‎llvm/lib/Target/RISCV/RISCVCombine.td

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//=- RISCVCombine.td - Define RISC-V Combine Rules -----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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def RISCVPreLegalizerCombiner: GICombiner<
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"RISCVPreLegalizerCombinerImpl", [all_combines]> {
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}
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def RISCVO0PreLegalizerCombiner: GICombiner<
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"RISCVO0PreLegalizerCombinerImpl", [optnone_combines]> {
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}

‎llvm/lib/Target/RISCV/RISCVGISel.td

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//===----------------------------------------------------------------------===//
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include "RISCV.td"
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include "RISCVCombine.td"
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def simm12Plus1 : ImmLeaf<XLenVT, [{
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return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;

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