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dtcxzywSForeKeeper
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SForeKeeper
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[RISCV] Add processor definition for XiangShan-NanHu (#70294)
This PR adds the processor definition for XiangShan-NanHu, an open-source high-performance RISC-V processor. According to the official [documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/), NanHu core supports `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval`. I found that NanHu also supports `zicbom` and `zicboz`. You can find them in the [source code](https://github.com/OpenXiangShan/XiangShan/blob/5931ace35325a644a12f8ea27830a2de7489e7e7/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L426-L436). Features supported by NanHu have been confirmed by @poemonsense. --------- Co-authored-by: SForeKeeper <[email protected]>
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‎clang/test/Driver/riscv-cpus.c

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// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
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// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
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// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+c"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zicbom" "-target-feature" "+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbkx" "-target-feature" "+zbs"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zkn" "-target-feature" "+zknd" "-target-feature" "+zkne" "-target-feature" "+zknh"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
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// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
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// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
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// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
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// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s
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// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
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// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
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// Check mtune alias CPU has resolved to the right CPU according XLEN.
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s
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// MTUNE-GENERIC-32: "-tune-cpu" "generic"

‎clang/test/Misc/target-invalid-cpu-note.c

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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1{{$}}
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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FeatureStdExtZicboz,
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FeatureVendorXVentanaCondOps],
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[TuneVentanaVeyron]>;
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def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbc,
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FeatureStdExtZbs,
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FeatureStdExtZkn,
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FeatureStdExtZksed,
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FeatureStdExtZksh,
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FeatureStdExtSvinval,
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FeatureStdExtZicbom,
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FeatureStdExtZicboz]>;

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