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alexey-bataevalexey-bataev
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[SLP][NFC]Add a test with the skipped gather node, which is same, as vectorized node.
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‎llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 < %s | FileCheck %s
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%struct.rect = type { float, float, float, float }
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define void @foo(ptr %i7, i32 %0, i1 %tobool62.not) {
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; CHECK-LABEL: define void @foo(
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; CHECK-SAME: ptr [[I7:%.*]], i32 [[TMP0:%.*]], i1 [[TOBOOL62_NOT:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RC21:%.*]] = alloca [0 x [0 x %struct.rect]], i32 0, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[RC21]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x float>
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; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 0>
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; CHECK-NEXT: [[X1:%.*]] = getelementptr i8, ptr [[RC21]], i64 4
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; CHECK-NEXT: [[TMP6:%.*]] = load <2 x float>, ptr [[X1]], align 4
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; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[I7]], align 4
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
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; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> [[TMP9]], <4 x i32> <i32 0, i32 4, i32 5, i32 poison>
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; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP7]], i32 3
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; CHECK-NEXT: [[TMP12:%.*]] = fcmp olt <4 x float> [[TMP11]], zeroinitializer
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; CHECK-NEXT: [[TMP13:%.*]] = load <4 x float>, ptr poison, align 16
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; CHECK-NEXT: [[TMP14:%.*]] = fcmp olt <4 x float> [[TMP13]], zeroinitializer
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; CHECK-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP14]], <4 x float> [[TMP5]], <4 x float> zeroinitializer
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; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP12]], <4 x float> zeroinitializer, <4 x float> [[TMP15]]
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; CHECK-NEXT: store <4 x float> [[TMP16]], ptr [[RC21]], align 4
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; CHECK-NEXT: br label [[IF_END:%.*]]
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; CHECK: entry.if.end72_crit_edge:
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; CHECK-NEXT: br label [[IF_END72:%.*]]
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; CHECK: if.then63:
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; CHECK-NEXT: br label [[IF_END]]
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; CHECK: if.end:
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; CHECK-NEXT: [[TMP17:%.*]] = phi <4 x float> [ poison, [[IF_THEN63:%.*]] ], [ [[TMP16]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP18:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[TMP17]])
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; CHECK-NEXT: [[TMP19:%.*]] = fptosi <4 x float> [[TMP18]] to <4 x i32>
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; CHECK-NEXT: br label [[IF_END72]]
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; CHECK: if.end72:
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; CHECK-NEXT: [[TMP20:%.*]] = phi <4 x i32> [ poison, [[ENTRY_IF_END72_CRIT_EDGE:%.*]] ], [ [[TMP19]], [[IF_END]] ]
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; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP20]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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; CHECK-NEXT: br i1 [[TOBOOL62_NOT]], label [[IF_END75:%.*]], label [[IF_THEN74:%.*]]
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; CHECK: if.then74:
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; CHECK-NEXT: br label [[IF_END75]]
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; CHECK: if.end75:
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; CHECK-NEXT: [[TMP22:%.*]] = phi <4 x i32> [ [[TMP20]], [[IF_THEN74]] ], [ [[TMP21]], [[IF_END72]] ]
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; CHECK-NEXT: [[TMP23:%.*]] = or <4 x i32> [[TMP22]], <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP25:%.*]] = mul <4 x i32> [[TMP23]], [[TMP24]]
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; CHECK-NEXT: [[TMP26:%.*]] = sitofp <4 x i32> [[TMP25]] to <4 x float>
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; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <4 x float> [[TMP26]], <4 x float> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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; CHECK-NEXT: store <4 x float> [[TMP27]], ptr [[RC21]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%rc21 = alloca [0 x [0 x %struct.rect]], i32 0, align 4
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%1 = load float, ptr %rc21, align 4
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%cmp = fcmp olt float %1, 0.000000e+00
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%conv = sitofp i32 %0 to float
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%cmp2 = fcmp olt float %conv, 0.000000e+00
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%cond = select i1 %cmp2, float %conv, float 0.000000e+00
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%cond9 = select i1 %cmp, float 0.000000e+00, float %cond
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store float %cond9, ptr %rc21, align 4
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%x1 = getelementptr i8, ptr %rc21, i64 4
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%2 = load float, ptr %x1, align 4
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%cmp11 = fcmp olt float %2, 0.000000e+00
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%conv16 = sitofp i32 %0 to float
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%cmp17 = fcmp olt float %conv16, 0.000000e+00
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%cond24 = select i1 %cmp17, float %conv16, float 0.000000e+00
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%cond26 = select i1 %cmp11, float 0.000000e+00, float %cond24
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store float %cond26, ptr %x1, align 4
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%y0 = getelementptr i8, ptr %rc21, i64 8
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%3 = load float, ptr %y0, align 4
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%cmp28 = fcmp olt float %3, 0.000000e+00
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%cmp34 = fcmp olt float %conv, 0.000000e+00
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%cond41 = select i1 %cmp34, float %conv, float 0.000000e+00
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%cond43 = select i1 %cmp28, float 0.000000e+00, float %cond41
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store float %cond43, ptr %y0, align 4
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%y11 = getelementptr i8, ptr %rc21, i64 12
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%4 = load float, ptr %i7, align 4
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%cmp45 = fcmp olt float %4, 0.000000e+00
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%cmp51 = fcmp olt float %conv16, 0.000000e+00
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%cond58 = select i1 %cmp51, float %conv16, float 0.000000e+00
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%cond60 = select i1 %cmp45, float 0.000000e+00, float %cond58
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store float %cond60, ptr %y11, align 4
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br label %if.end
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entry.if.end72_crit_edge:
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br label %if.end72
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if.then63:
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br label %if.end
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if.end:
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%5 = phi float [ 0.000000e+00, %if.then63 ], [ %cond60, %entry ]
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%6 = phi float [ 0.000000e+00, %if.then63 ], [ %cond26, %entry ]
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%7 = phi float [ 0.000000e+00, %if.then63 ], [ %cond43, %entry ]
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%8 = phi float [ 0.000000e+00, %if.then63 ], [ %cond9, %entry ]
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%9 = call float @llvm.round.f32(float %8)
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%conv65 = fptosi float %9 to i32
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%10 = call float @llvm.round.f32(float %7)
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%conv67 = fptosi float %10 to i32
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%11 = call float @llvm.round.f32(float %6)
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%conv69 = fptosi float %11 to i32
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%12 = call float @llvm.round.f32(float %5)
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%conv71 = fptosi float %12 to i32
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br label %if.end72
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if.end72:
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%.pre100 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv71, %if.end ]
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%.pre99 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv67, %if.end ]
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%.pre98 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv69, %if.end ]
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%.pre97 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv65, %if.end ]
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br i1 %tobool62.not, label %if.end75, label %if.then74
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if.then74:
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br label %if.end75
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if.end75:
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%13 = phi i32 [ %.pre99, %if.then74 ], [ %.pre100, %if.end72 ]
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%14 = phi i32 [ %.pre100, %if.then74 ], [ %.pre99, %if.end72 ]
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%15 = phi i32 [ %.pre97, %if.then74 ], [ %.pre98, %if.end72 ]
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%16 = phi i32 [ %.pre98, %if.then74 ], [ %.pre97, %if.end72 ]
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%sub = or i32 %16, 1
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%mul = mul i32 %sub, %0
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%conv77 = sitofp i32 %mul to float
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store float %conv77, ptr %rc21, align 4
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%x178 = getelementptr i8, ptr %rc21, i64 4
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%sub79 = or i32 %15, 1
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%mul80 = mul i32 %sub79, %0
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%conv81 = sitofp i32 %mul80 to float
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store float %conv81, ptr %x178, align 4
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%y082 = getelementptr i8, ptr %rc21, i64 8
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%sub83 = or i32 %14, 1
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%mul84 = mul i32 %sub83, %0
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%conv85 = sitofp i32 %mul84 to float
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store float %conv85, ptr %y082, align 4
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%y186 = getelementptr i8, ptr %rc21, i64 12
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%sub87 = or i32 %13, 1
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%mul88 = mul i32 %sub87, %0
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%conv89 = sitofp i32 %mul88 to float
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store float %conv89, ptr %y186, align 4
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ret void
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}

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