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[WebAssembly] Format WebAssembly ReleaseNote entries (#122203)
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llvm/docs/ReleaseNotes.md

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@@ -240,15 +240,15 @@ Changes to the RISC-V Backend
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Changes to the WebAssembly Backend
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The default target CPU, "generic", now enables the `-mnontrapping-fptoint`
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and `-mbulk-memory` flags, which correspond to the [Bulk Memory Operations]
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and [Non-trapping float-to-int Conversions] language features, which are
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[widely implemented in engines].
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A new Lime1 target CPU is added, -mcpu=lime1. This CPU follows the definition of
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the Lime1 CPU [here], and enables -mmultivalue, -mmutable-globals,
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-mcall-indirect-overlong, -msign-ext, -mbulk-memory-opt, -mnontrapping-fptoint,
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and -mextended-const.
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* The default target CPU, "generic", now enables the `-mnontrapping-fptoint`
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and `-mbulk-memory` flags, which correspond to the [Bulk Memory Operations]
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and [Non-trapping float-to-int Conversions] language features, which are
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[widely implemented in engines].
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* A new Lime1 target CPU is added, `-mcpu=lime1`. This CPU follows the
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definition of the Lime1 CPU [here], and enables `-mmultivalue`,
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`-mmutable-globals`, `-mcall-indirect-overlong`, `-msign-ext`,
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`-mbulk-memory-opt`, `-mnontrapping-fptoint`, and `-mextended-const`.
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[Bulk Memory Operations]: https://github.com/WebAssembly/bulk-memory-operations/blob/master/proposals/bulk-memory-operations/Overview.md
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[Non-trapping float-to-int Conversions]: https://github.com/WebAssembly/spec/blob/master/proposals/nontrapping-float-to-int-conversion/Overview.md

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