CodeGen: Eliminate dynamic relocations in the register superclass tables.

Author: resistor

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -46,7 +46,7 @@ class TargetRegisterClass {
 public:
   using iterator = const MCPhysReg *;
   using const_iterator = const MCPhysReg *;
-  using sc_iterator = const TargetRegisterClass* const *;
+  using sc_iterator = const unsigned *;
 
   // Instance variables filled by tablegen, do not use!
   const MCRegisterClass *MC;
@@ -184,9 +184,7 @@ class TargetRegisterClass {
 
   /// Return true if this TargetRegisterClass is a subset
   /// class of at least one other TargetRegisterClass.
-  bool isASubClass() const {
-    return SuperClasses[0] != nullptr;
-  }
+  bool isASubClass() const { return SuperClasses[0] != ~0U; }
 
   /// Returns the preferred order for allocating registers from this register
   /// class in MF. The raw order comes directly from the .td file and may

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

@@ -262,30 +262,30 @@ bool ARMBaseRegisterInfo::isInlineAsmReadOnlyReg(const MachineFunction &MF,
 const TargetRegisterClass *
 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
                                                const MachineFunction &MF) const {
-  const TargetRegisterClass *Super = RC;
+  unsigned SuperID = RC->getID();
   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
   do {
-    switch (Super->getID()) {
+    switch (SuperID) {
     case ARM::GPRRegClassID:
     case ARM::SPRRegClassID:
     case ARM::DPRRegClassID:
     case ARM::GPRPairRegClassID:
-      return Super;
+      return getRegClass(SuperID);
     case ARM::QPRRegClassID:
     case ARM::QQPRRegClassID:
     case ARM::QQQQPRRegClassID:
       if (MF.getSubtarget<ARMSubtarget>().hasNEON())
-        return Super;
+        return getRegClass(SuperID);
       break;
     case ARM::MQPRRegClassID:
     case ARM::MQQPRRegClassID:
     case ARM::MQQQQPRRegClassID:
       if (MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps())
-        return Super;
+        return getRegClass(SuperID);
       break;
     }
-    Super = *I++;
-  } while (Super);
+    SuperID = *I++;
+  } while (SuperID != ~0U);
   return RC;
 }
 

llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp

@@ -431,8 +431,9 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
       return WSub[GenIdx];
   }
 
-  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
-    return getHexagonSubRegIndex(*SuperRC, GenIdx);
+  unsigned SuperID = *RC.getSuperClasses();
+  if (SuperID != ~0U)
+    return getHexagonSubRegIndex(*getRegClass(SuperID), GenIdx);
 
   llvm_unreachable("Invalid register class");
 }

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

@@ -692,21 +692,22 @@ PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
         InflateGPRC++;
     }
 
-    for (const auto *I = RC->getSuperClasses(); *I; ++I) {
-      if (getRegSizeInBits(**I) != getRegSizeInBits(*RC))
+    for (const unsigned *I = RC->getSuperClasses(); *I != ~0U; ++I) {
+      if (getRegSizeInBits(*getRegClass(*I)) != getRegSizeInBits(*RC))
         continue;
 
-      switch ((*I)->getID()) {
+      switch (*I) {
       case PPC::VSSRCRegClassID:
-        return Subtarget.hasP8Vector() ? *I : DefaultSuperclass;
+        return Subtarget.hasP8Vector() ? getRegClass(*I) : DefaultSuperclass;
       case PPC::VSFRCRegClassID:
       case PPC::VSRCRegClassID:
-        return *I;
+        return getRegClass(*I);
       case PPC::VSRpRCRegClassID:
-        return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass;
+        return Subtarget.pairedVectorMemops() ? getRegClass(*I)
+                                              : DefaultSuperclass;
       case PPC::ACCRCRegClassID:
       case PPC::UACCRCRegClassID:
-        return Subtarget.hasMMA() ? *I : DefaultSuperclass;
+        return Subtarget.hasMMA() ? getRegClass(*I) : DefaultSuperclass;
       }
     }
   }

llvm/lib/Target/X86/X86RegisterInfo.cpp

@@ -172,7 +172,8 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
         return Super;
     }
-    Super = *I++;
+    Super = (*I != ~0U) ? getRegClass(*I) : nullptr;
+    ++I;
   } while (Super);
   return RC;
 }

llvm/utils/TableGen/RegisterInfoEmitter.cpp

@@ -1286,8 +1286,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
     }
     OS << "};\n";
 
-    OS << "\nstatic const TargetRegisterClass *const "
-       << "NullRegClasses[] = { nullptr };\n\n";
+    OS << "\nstatic const unsigned "
+       << "NullRegClasses[] = { ~0U };\n\n";
 
     // Emit register class bit mask tables. The first bit mask emitted for a
     // register class, RC, is the set of sub-classes, including RC itself.
@@ -1348,11 +1348,10 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
       if (Supers.empty())
         continue;
 
-      OS << "static const TargetRegisterClass *const " << RC.getName()
-         << "Superclasses[] = {\n";
+      OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n";
       for (const auto *Super : Supers)
-        OS << "  &" << Super->getQualifiedName() << "RegClass,\n";
-      OS << "  nullptr\n};\n\n";
+        OS << "  " << Super->getQualifiedIdName() << ",\n";
+      OS << "  ~0U\n};\n\n";
     }
 
     // Emit methods.