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1 parent 7317a6e commit 87cc4b4Copy full SHA for 87cc4b4
llvm/test/MachineVerifier/RISCV/subreg-liveness.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s
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+# REQUIRES: riscv64-registered-target
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# During the MachineVerifier, it assumes that used registers have been defined
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# In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15,
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