[LLVM][AArch64] Correctly lower funnel shifts by zero.

Prevent LowerFunnelShift from creating an invalid ISD::FSHR when
lowering "ISD::FSHL X, Y, 0". Such inputs are rare because it's a NOP
that DAGCombiner will optimise away. However, we shoudl not rely on
this and so this PR mirror the same optimisation.

NOTE: To simiplify testing, this PR also adds a command line option
to disable the DAG combiner (-combiner-disabled).

Author: paulwalker-arm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -7266,12 +7266,18 @@ static SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) {
     MVT VT = Op.getSimpleValueType();
 
     if (Op.getOpcode() == ISD::FSHL) {
+      if (ShiftNo->isZero())
+        return Op.getOperand(0);
+
       unsigned int NewShiftNo =
           VT.getFixedSizeInBits() - ShiftNo->getZExtValue();
       return DAG.getNode(
           ISD::FSHR, DL, VT, Op.getOperand(0), Op.getOperand(1),
           DAG.getConstant(NewShiftNo, DL, Shifts.getValueType()));
     } else if (Op.getOpcode() == ISD::FSHR) {
+      if (ShiftNo->isZero())
+        return Op.getOperand(1);
+
       return Op;
     }
   }