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[RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to remove i32 from the GPR register class. RORW/ROLW target opcodes are added to match SelectionDAG. The regression in rv64zbb-zbkb.ll requires factoring isSExtCheaperThanZExt into the G_ANYEXT constant folder. That requires some interface changes so I didn't do it in this patch.
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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -203,8 +203,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
203203
getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
204204

205205
getActionDefinitionsBuilder({G_ROTL, G_ROTR})
206-
.legalFor(ST.hasStdExtZbb() || ST.hasStdExtZbkb(),
207-
{{s32, s32}, {sXLen, sXLen}})
206+
.legalFor(ST.hasStdExtZbb() || ST.hasStdExtZbkb(), {{sXLen, sXLen}})
207+
.customFor(ST.is64Bit() && (ST.hasStdExtZbb() || ST.hasStdExtZbkb()),
208+
{{s32, s32}})
208209
.lower();
209210

210211
getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();
@@ -1162,6 +1163,10 @@ static unsigned getRISCVWOpcode(unsigned Opcode) {
11621163
switch (Opcode) {
11631164
default:
11641165
llvm_unreachable("Unexpected opcode");
1166+
case TargetOpcode::G_ROTL:
1167+
return RISCV::G_ROLW;
1168+
case TargetOpcode::G_ROTR:
1169+
return RISCV::G_RORW;
11651170
case TargetOpcode::G_CTLZ:
11661171
return RISCV::G_CLZW;
11671172
case TargetOpcode::G_CTTZ:
@@ -1205,6 +1210,16 @@ bool RISCVLegalizerInfo::legalizeCustom(
12051210
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
12061211
LegalizerHelper::Legalized;
12071212
}
1213+
case TargetOpcode::G_ROTL:
1214+
case TargetOpcode::G_ROTR: {
1215+
Helper.Observer.changingInstr(MI);
1216+
Helper.widenScalarSrc(MI, sXLen, 1, TargetOpcode::G_ANYEXT);
1217+
Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ANYEXT);
1218+
Helper.widenScalarDst(MI, sXLen);
1219+
MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
1220+
Helper.Observer.changedInstr(MI);
1221+
return true;
1222+
}
12081223
case TargetOpcode::G_CTLZ:
12091224
case TargetOpcode::G_CTTZ: {
12101225
Helper.Observer.changingInstr(MI);

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -274,14 +274,6 @@ let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
274274
def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
275275
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
276276
def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
277-
278-
def : PatGprGpr<rotl, ROLW, i32, i32>;
279-
def : PatGprGpr<rotr, RORW, i32, i32>;
280-
def : Pat<(i32 (rotr GPR:$rs1, uimm5i32:$imm)),
281-
(RORIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
282-
283-
def : Pat<(i32 (rotl GPR:$rs1, uimm5i32:$rs2)),
284-
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5i32:$rs2))>;
285277
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
286278

287279
let Predicates = [HasStdExtZba, IsRV64] in {

‎llvm/lib/Target/RISCV/RISCVInstrGISel.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,22 @@ class RISCVGenericInstruction : GenericInstruction {
1717
let Namespace = "RISCV";
1818
}
1919

20+
// Pseudo equivalent to a RISCVISD::RORW.
21+
def G_RORW : RISCVGenericInstruction {
22+
let OutOperandList = (outs type0:$dst);
23+
let InOperandList = (ins type0:$src1, type0:$src2);
24+
let hasSideEffects = false;
25+
}
26+
def : GINodeEquiv<G_RORW, riscv_rorw>;
27+
28+
// Pseudo equivalent to a RISCVISD::ROLW.
29+
def G_ROLW : RISCVGenericInstruction {
30+
let OutOperandList = (outs type0:$dst);
31+
let InOperandList = (ins type0:$src1, type0:$src2);
32+
let hasSideEffects = false;
33+
}
34+
def : GINodeEquiv<G_ROLW, riscv_rolw>;
35+
2036
// Pseudo equivalent to a RISCVISD::CLZW.
2137
def G_CLZW : RISCVGenericInstruction {
2238
let OutOperandList = (outs type0:$dst);

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir

Lines changed: 12 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -22,12 +22,9 @@ body: |
2222
; CHECK-NEXT: $x10 = COPY [[ROLW]]
2323
; CHECK-NEXT: PseudoRET implicit $x10
2424
%0:gprb(s64) = COPY $x10
25-
%1:gprb(s32) = G_TRUNC %0(s64)
26-
%2:gprb(s64) = COPY $x11
27-
%6:gprb(s32) = G_TRUNC %2(s64)
28-
%4:gprb(s32) = G_ROTL %1, %6(s32)
29-
%5:gprb(s64) = G_ANYEXT %4(s32)
30-
$x10 = COPY %5(s64)
25+
%1:gprb(s64) = COPY $x11
26+
%2:gprb(s64) = G_ROLW %0, %1(s64)
27+
$x10 = COPY %2(s64)
3128
PseudoRET implicit $x10
3229
3330
...
@@ -72,12 +69,9 @@ body: |
7269
; CHECK-NEXT: $x10 = COPY [[RORW]]
7370
; CHECK-NEXT: PseudoRET implicit $x10
7471
%0:gprb(s64) = COPY $x10
75-
%1:gprb(s32) = G_TRUNC %0(s64)
76-
%2:gprb(s64) = COPY $x11
77-
%6:gprb(s32) = G_TRUNC %2(s64)
78-
%4:gprb(s32) = G_ROTR %1, %6(s32)
79-
%5:gprb(s64) = G_ANYEXT %4(s32)
80-
$x10 = COPY %5(s64)
72+
%1:gprb(s64) = COPY $x11
73+
%2:gprb(s64) = G_RORW %0, %1(s64)
74+
$x10 = COPY %2(s64)
8175
PseudoRET implicit $x10
8276
8377
...
@@ -121,11 +115,9 @@ body: |
121115
; CHECK-NEXT: $x10 = COPY [[RORIW]]
122116
; CHECK-NEXT: PseudoRET implicit $x10
123117
%0:gprb(s64) = COPY $x10
124-
%1:gprb(s32) = G_TRUNC %0(s64)
125-
%2:gprb(s32) = G_CONSTANT i32 15
126-
%3:gprb(s32) = G_ROTL %1, %2(s32)
127-
%4:gprb(s64) = G_ANYEXT %3(s32)
128-
$x10 = COPY %4(s64)
118+
%1:gprb(s64) = G_CONSTANT i64 15
119+
%2:gprb(s64) = G_ROLW %0, %1(s64)
120+
$x10 = COPY %2(s64)
129121
PseudoRET implicit $x10
130122
131123
...
@@ -169,11 +161,9 @@ body: |
169161
; CHECK-NEXT: $x10 = COPY [[RORIW]]
170162
; CHECK-NEXT: PseudoRET implicit $x10
171163
%0:gprb(s64) = COPY $x10
172-
%1:gprb(s32) = G_TRUNC %0(s64)
173-
%2:gprb(s32) = G_CONSTANT i32 15
174-
%3:gprb(s32) = G_ROTR %1, %2(s32)
175-
%4:gprb(s64) = G_ANYEXT %3(s32)
176-
$x10 = COPY %4(s64)
164+
%1:gprb(s64) = G_CONSTANT i64 15
165+
%2:gprb(s64) = G_RORW %0, %1(s64)
166+
$x10 = COPY %2(s64)
177167
PseudoRET implicit $x10
178168
179169
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -109,12 +109,9 @@ body: |
109109
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
110110
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
111111
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
112-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
113112
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
114-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
115-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[TRUNC1]](s32)
116-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTL]](s32)
117-
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
113+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROLW:%[0-9]+]]:_(s64) = G_ROLW [[COPY]], [[COPY1]]
114+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROLW]](s64)
118115
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
119116
%2:_(s64) = COPY $x10
120117
%0:_(s32) = G_TRUNC %2(s64)
@@ -268,12 +265,9 @@ body: |
268265
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
269266
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
270267
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
271-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
272268
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
273-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
274-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[TRUNC1]](s32)
275-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTR]](s32)
276-
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
269+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[RORW:%[0-9]+]]:_(s64) = G_RORW [[COPY]], [[COPY1]]
270+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[RORW]](s64)
277271
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
278272
%2:_(s64) = COPY $x10
279273
%0:_(s32) = G_TRUNC %2(s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,9 @@ define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
166166
;
167167
; RV64ZBB-ZBKB-LABEL: rol_i32_neg_constant_rhs:
168168
; RV64ZBB-ZBKB: # %bb.0:
169-
; RV64ZBB-ZBKB-NEXT: li a1, -2
169+
; RV64ZBB-ZBKB-NEXT: li a1, 1
170+
; RV64ZBB-ZBKB-NEXT: slli a1, a1, 32
171+
; RV64ZBB-ZBKB-NEXT: addi a1, a1, -2
170172
; RV64ZBB-ZBKB-NEXT: rolw a0, a1, a0
171173
; RV64ZBB-ZBKB-NEXT: ret
172174
%1 = tail call i32 @llvm.fshl.i32(i32 -2, i32 -2, i32 %a)
@@ -250,7 +252,9 @@ define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
250252
;
251253
; RV64ZBB-ZBKB-LABEL: ror_i32_neg_constant_rhs:
252254
; RV64ZBB-ZBKB: # %bb.0:
253-
; RV64ZBB-ZBKB-NEXT: li a1, -2
255+
; RV64ZBB-ZBKB-NEXT: li a1, 1
256+
; RV64ZBB-ZBKB-NEXT: slli a1, a1, 32
257+
; RV64ZBB-ZBKB-NEXT: addi a1, a1, -2
254258
; RV64ZBB-ZBKB-NEXT: rorw a0, a1, a0
255259
; RV64ZBB-ZBKB-NEXT: ret
256260
%1 = tail call i32 @llvm.fshr.i32(i32 -2, i32 -2, i32 %a)

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