[RISCV][GISEL] Legalize and regbankselect vector typed G_IMPLICIT_DEF

Author: michaelmaitland

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -107,7 +107,6 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
 
   using namespace TargetOpcode;
 
-  
   auto BoolVecTys = {nxv1s1, nxv2s1, nxv4s1, nxv8s1, nxv16s1, nxv32s1, nxv64s1};
 
   auto IntOrFPVecTys = {nxv1s8,   nxv2s8,  nxv4s8,  nxv8s8,  nxv16s8, nxv32s8,
@@ -217,6 +216,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
 
   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
       .legalFor({s32, sXLen, p0})
+      .legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
+      .legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
       .widenScalarToNextPow2(0)
       .clampScalar(0, s32, sXLen);
 

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -351,6 +351,11 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     // $f10_d = COPY %1(s32)
     if (anyUseOnlyUseFP(Dst, MRI, TRI))
       Mapping = getFPValueMapping(MRI.getType(Dst).getSizeInBits());
+
+    LLT DstTy = MRI.getType(Dst);
+    if (DstTy.isVector())
+      Mapping = getVRBValueMapping(DstTy.getSizeInBits().getKnownMinValue());
+
     return getInstructionMapping(DefaultMappingID, /*Cost=*/1, Mapping,
                                  NumOperands);
   }