@@ -1021,3 +1021,77 @@ define <8 x i32> @shuffle_repeat4_singlesrc_e32(<8 x i32> %v) {
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%out = shufflevector <8 x i32 > %v , <8 x i32 > poison, <8 x i32 > <i32 0 , i32 0 , i32 0 , i32 0 , i32 1 , i32 1 , i32 1 , i32 1 >
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ret <8 x i32 > %out
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}
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+
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+ define <16 x i32 > @shuffle_disjoint_lanes (<16 x i32 > %v , <16 x i32 > %w ) {
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+ ; CHECK-LABEL: shuffle_disjoint_lanes:
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+ ; CHECK: # %bb.0:
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+ ; CHECK-NEXT: lui a0, %hi(.LCPI70_0)
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+ ; CHECK-NEXT: addi a0, a0, %lo(.LCPI70_0)
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+ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
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+ ; CHECK-NEXT: vle16.v v20, (a0)
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+ ; CHECK-NEXT: lui a0, %hi(.LCPI70_1)
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+ ; CHECK-NEXT: addi a0, a0, %lo(.LCPI70_1)
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+ ; CHECK-NEXT: vle16.v v22, (a0)
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+ ; CHECK-NEXT: lui a0, 15
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+ ; CHECK-NEXT: addi a0, a0, 240
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+ ; CHECK-NEXT: vmv.s.x v0, a0
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+ ; CHECK-NEXT: vrgatherei16.vv v16, v8, v20
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+ ; CHECK-NEXT: vrgatherei16.vv v16, v12, v22, v0.t
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+ ; CHECK-NEXT: vmv.v.v v8, v16
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+ ; CHECK-NEXT: ret
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+ %out = shufflevector <16 x i32 > %v , <16 x i32 > %w , <16 x i32 > <i32 11 , i32 15 , i32 7 , i32 3 , i32 26 , i32 30 , i32 22 , i32 18 , i32 9 , i32 13 , i32 5 , i32 1 , i32 24 , i32 28 , i32 20 , i32 16 >
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+ ret <16 x i32 > %out
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+ }
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+
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+ define <16 x i32 > @shuffle_disjoint_lanes_one_identity (<16 x i32 > %v , <16 x i32 > %w ) {
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+ ; CHECK-LABEL: shuffle_disjoint_lanes_one_identity:
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+ ; CHECK: # %bb.0:
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+ ; CHECK-NEXT: lui a0, %hi(.LCPI71_0)
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+ ; CHECK-NEXT: addi a0, a0, %lo(.LCPI71_0)
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+ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
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+ ; CHECK-NEXT: vle16.v v16, (a0)
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+ ; CHECK-NEXT: li a0, -272
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+ ; CHECK-NEXT: vmv.s.x v0, a0
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+ ; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t
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+ ; CHECK-NEXT: ret
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+ %out = shufflevector <16 x i32 > %v , <16 x i32 > %w , <16 x i32 > <i32 0 , i32 1 , i32 2 , i32 3 , i32 26 , i32 30 , i32 22 , i32 20 , i32 8 , i32 31 , i32 29 , i32 28 , i32 27 , i32 23 , i32 25 , i32 22 >
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+ ret <16 x i32 > %out
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+ }
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+
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+ define <16 x i32 > @shuffle_disjoint_lanes_one_broadcast (<16 x i32 > %v , <16 x i32 > %w ) {
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+ ; CHECK-LABEL: shuffle_disjoint_lanes_one_broadcast:
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+ ; CHECK: # %bb.0:
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+ ; CHECK-NEXT: lui a0, %hi(.LCPI72_0)
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+ ; CHECK-NEXT: addi a0, a0, %lo(.LCPI72_0)
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+ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
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+ ; CHECK-NEXT: vle16.v v20, (a0)
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+ ; CHECK-NEXT: lui a0, 15
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+ ; CHECK-NEXT: addi a0, a0, 240
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+ ; CHECK-NEXT: vmv.s.x v0, a0
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+ ; CHECK-NEXT: vrgather.vi v16, v8, 7
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+ ; CHECK-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
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+ ; CHECK-NEXT: vmv.v.v v8, v16
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+ ; CHECK-NEXT: ret
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+ %out = shufflevector <16 x i32 > %v , <16 x i32 > %w , <16 x i32 > <i32 7 , i32 7 , i32 7 , i32 7 , i32 26 , i32 30 , i32 22 , i32 18 , i32 7 , i32 7 , i32 7 , i32 7 , i32 24 , i32 28 , i32 20 , i32 16 >
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+ ret <16 x i32 > %out
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+ }
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+
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+ define <16 x i32 > @shuffle_disjoint_lanes_one_splat (i32 %v , <16 x i32 > %w ) {
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+ ; CHECK-LABEL: shuffle_disjoint_lanes_one_splat:
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+ ; CHECK: # %bb.0:
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+ ; CHECK-NEXT: lui a1, %hi(.LCPI73_0)
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+ ; CHECK-NEXT: addi a1, a1, %lo(.LCPI73_0)
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+ ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
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+ ; CHECK-NEXT: vle16.v v16, (a1)
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+ ; CHECK-NEXT: lui a1, 15
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+ ; CHECK-NEXT: addi a1, a1, 240
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+ ; CHECK-NEXT: vmv.s.x v0, a1
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+ ; CHECK-NEXT: vmv.v.x v12, a0
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+ ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
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+ ; CHECK-NEXT: vmv.v.v v8, v12
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+ ; CHECK-NEXT: ret
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+ %head = insertelement <16 x i32 > poison, i32 %v , i32 0
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+ %splat = shufflevector <16 x i32 > %head , <16 x i32 > poison, <16 x i32 > zeroinitializer
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+ %out = shufflevector <16 x i32 > %splat , <16 x i32 > %w , <16 x i32 > <i32 11 , i32 15 , i32 7 , i32 3 , i32 26 , i32 30 , i32 22 , i32 18 , i32 9 , i32 13 , i32 5 , i32 1 , i32 24 , i32 28 , i32 20 , i32 16 >
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+ ret <16 x i32 > %out
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+ }
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