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[RISCV] Support Zb*/P Shared Instructions (#127160)
This enables shared instructions between Zb* and Base-P extension. Documentation: https://jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-014.pdf
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-13
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8 files changed

+133
-13
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‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -182,6 +182,7 @@
182182
// CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes)
183183
// CHECK-EMPTY:
184184
// CHECK-NEXT: Experimental extensions
185+
// CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD))
185186
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
186187
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
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// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1016,6 +1016,39 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
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"'Smctr' (Control Transfer Records Machine Level) or "
10171017
"'Ssctr' (Control Transfer Records Supervisor Level)">;
10181018

1019+
// Packed SIMD Extensions
1020+
def FeatureStdExtP
1021+
: RISCVExperimentalExtension<0, 14,
1022+
"'Base P' (Packed SIMD)">;
1023+
def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
1024+
AssemblerPredicate<(all_of FeatureStdExtP),
1025+
"'Base P' (Packed SIMD)">;
1026+
1027+
def HasStdExtZbaOrP
1028+
: Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">,
1029+
AssemblerPredicate<(any_of FeatureStdExtZba, FeatureStdExtP),
1030+
"'Zba' (Address Generation Instructions) or "
1031+
"'Base P' (Packed-SIMD)">;
1032+
1033+
def HasStdExtZbbOrP
1034+
: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtP()">,
1035+
AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtP),
1036+
"'Zbb' (Basic Bit-Manipulation) or "
1037+
"'Base P' (Packed-SIMD)">;
1038+
1039+
def HasStdExtZbkbOrP
1040+
: Predicate<"Subtarget->hasStdExtZbkb() || Subtarget->hasStdExtP()">,
1041+
AssemblerPredicate<(any_of FeatureStdExtZbkb, FeatureStdExtP),
1042+
"'Zbkb' (Bitmanip instructions for Cryptography) or "
1043+
"'Base P' (Packed-SIMD)">;
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1045+
def HasStdExtZbbOrZbkbOrP
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: Predicate<"Subtarget->HasStdExtZbbOrZbkb()|| Subtarget->hasStdExtP()">,
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AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP),
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"'Zbb' (Basic Bit-Manipulation) or "
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"'Zbkb' (Bitmanip instructions for Cryptography) or "
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"'Base P' (Packed-SIMD)">;
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//===----------------------------------------------------------------------===//
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// Vendor extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -263,9 +263,10 @@ def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
264264
} // Predicates = [HasStdExtZbbOrZbkb]
265265

266-
let Predicates = [HasStdExtZba] in {
266+
let Predicates = [HasStdExtZbaOrP] in
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def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
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Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
269+
let Predicates = [HasStdExtZba] in {
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def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">,
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Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
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def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
@@ -337,30 +338,32 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">,
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Sched<[WriteXPERM, ReadXPERM, ReadXPERM]>;
338339
} // Predicates = [HasStdExtZbkx]
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340-
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
341+
let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in
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def CLZ : Unary_r<0b011000000000, 0b001, "clz">,
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Sched<[WriteCLZ, ReadCLZ]>;
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let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
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def CTZ : Unary_r<0b011000000001, 0b001, "ctz">,
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Sched<[WriteCTZ, ReadCTZ]>;
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def CPOP : Unary_r<0b011000000010, 0b001, "cpop">,
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Sched<[WriteCPOP, ReadCPOP]>;
347349
} // Predicates = [HasStdExtZbb]
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349-
let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
351+
let Predicates = [HasStdExtZbbOrP, IsRV64], IsSignExtendingOpW = 1 in
350352
def CLZW : UnaryW_r<0b011000000000, 0b001, "clzw">,
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Sched<[WriteCLZ32, ReadCLZ32]>;
354+
let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
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def CTZW : UnaryW_r<0b011000000001, 0b001, "ctzw">,
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Sched<[WriteCTZ32, ReadCTZ32]>;
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def CPOPW : UnaryW_r<0b011000000010, 0b001, "cpopw">,
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Sched<[WriteCPOP32, ReadCPOP32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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358-
let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in {
361+
let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in {
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def SEXT_B : Unary_r<0b011000000100, 0b001, "sext.b">,
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Sched<[WriteIALU, ReadIALU]>;
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def SEXT_H : Unary_r<0b011000000101, 0b001, "sext.h">,
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Sched<[WriteIALU, ReadIALU]>;
363-
} // Predicates = [HasStdExtZbb]
366+
} // Predicates = [HasStdExtZbbOrP]
364367

365368
let Predicates = [HasStdExtZbc] in {
366369
def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", Commutable=1>,
@@ -374,7 +377,7 @@ def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", Commutable=1>,
374377
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
375378
} // Predicates = [HasStdExtZbcOrZbkc]
376379

377-
let Predicates = [HasStdExtZbb] in {
380+
let Predicates = [HasStdExtZbbOrP] in {
378381
def MIN : ALU_rr<0b0000101, 0b100, "min", Commutable=1>,
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Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
380383
def MINU : ALU_rr<0b0000101, 0b101, "minu", Commutable=1>,
@@ -385,9 +388,10 @@ def MAXU : ALU_rr<0b0000101, 0b111, "maxu", Commutable=1>,
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Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>;
386389
} // Predicates = [HasStdExtZbb]
387390

388-
let Predicates = [HasStdExtZbkb] in {
391+
let Predicates = [HasStdExtZbkbOrP] in
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def PACK : ALU_rr<0b0000100, 0b100, "pack">,
390393
Sched<[WritePACK, ReadPACK, ReadPACK]>;
394+
let Predicates = [HasStdExtZbkb] in {
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let IsSignExtendingOpW = 1 in
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def PACKH : ALU_rr<0b0000100, 0b111, "packh">,
393397
Sched<[WritePACK, ReadPACK, ReadPACK]>;
@@ -407,15 +411,15 @@ def ZEXT_H_RV64 : RVBUnaryR<0b0000100, 0b100, OPC_OP_32, "zext.h">,
407411
Sched<[WriteIALU, ReadIALU]>;
408412
} // Predicates = [HasStdExtZbb, IsRV64]
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410-
let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in {
414+
let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] in {
411415
def REV8_RV32 : Unary_r<0b011010011000, 0b101, "rev8">,
412416
Sched<[WriteREV8, ReadREV8]>;
413-
} // Predicates = [HasStdExtZbbOrZbkb, IsRV32]
417+
} // Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32]
414418

415-
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
419+
let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64] in {
416420
def REV8_RV64 : Unary_r<0b011010111000, 0b101, "rev8">,
417421
Sched<[WriteREV8, ReadREV8]>;
418-
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
422+
} // Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64]
419423

420424
let Predicates = [HasStdExtZbb] in {
421425
def ORC_B : Unary_r<0b001010000111, 0b101, "orc.b">,

‎llvm/test/MC/RISCV/attribute-arch.s

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@@ -473,3 +473,9 @@
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.attribute arch, "rv32i_sdtrig1p0"
475475
# CHECK: attribute 5, "rv32i2p1_sdtrig1p0"
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477+
.attribute arch, "rv32i_p0p14"
478+
# CHECK: attribute 5, "rv32i2p1_p0p14"
479+
480+
.attribute arch, "rv64i_p0p14"
481+
# CHECK: attribute 5, "rv64i2p1_p0p14"

‎llvm/test/MC/RISCV/rv32i-invalid.s

Lines changed: 2 additions & 2 deletions
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@@ -191,8 +191,8 @@ fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the followi
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fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}}
192192
fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}}
193193
flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
194-
sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions){{$}}
195-
clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}}
194+
sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) or 'Base P' (Packed-SIMD){{$}}
195+
clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) or 'Base P' (Packed-SIMD){{$}}
196196
clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}}
197197
bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}}
198198
pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}}

‎llvm/test/MC/RISCV/rv32p-valid.s

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@@ -0,0 +1,36 @@
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \
4+
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
5+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6+
7+
# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
8+
# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
9+
sh1add a0, a1, a2
10+
# CHECK-ASM-AND-OBJ: clz a0, a1
11+
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
12+
clz a0, a1
13+
# CHECK-ASM-AND-OBJ: sext.b a2, a3
14+
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
15+
sext.b a2, a3
16+
# CHECK-ASM-AND-OBJ: sext.h t0, t1
17+
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
18+
sext.h t0, t1
19+
# CHECK-ASM-AND-OBJ: min t0, t1, t2
20+
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
21+
min t0, t1, t2
22+
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
23+
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
24+
minu t0, t1, t2
25+
# CHECK-ASM-AND-OBJ: max t3, t4, t5
26+
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
27+
max t3, t4, t5
28+
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
29+
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
30+
maxu a4, a5, a6
31+
# CHECK-ASM-AND-OBJ: pack s0, s1, s2
32+
# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
33+
pack s0, s1, s2
34+
# CHECK-ASM-AND-OBJ: rev8 s0, s1
35+
# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69]
36+
rev8 s0, s1

‎llvm/test/MC/RISCV/rv64p-valid.s

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -riscv-no-aliases -show-encoding \
2+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-p < %s \
4+
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r - \
5+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6+
7+
# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2
8+
# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20]
9+
sh1add a0, a1, a2
10+
# CHECK-ASM-AND-OBJ: clz a0, a1
11+
# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60]
12+
clz a0, a1
13+
# CHECK-ASM-AND-OBJ: clzw s0, s1
14+
# CHECK-ASM: encoding: [0x1b,0x94,0x04,0x60]
15+
clzw s0, s1
16+
# CHECK-ASM-AND-OBJ: sext.b a2, a3
17+
# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60]
18+
sext.b a2, a3
19+
# CHECK-ASM-AND-OBJ: sext.h t0, t1
20+
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
21+
sext.h t0, t1
22+
# CHECK-ASM-AND-OBJ: min t0, t1, t2
23+
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
24+
min t0, t1, t2
25+
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
26+
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
27+
minu t0, t1, t2
28+
# CHECK-ASM-AND-OBJ: max t3, t4, t5
29+
# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b]
30+
max t3, t4, t5
31+
# CHECK-ASM-AND-OBJ: maxu a4, a5, a6
32+
# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b]
33+
maxu a4, a5, a6
34+
# CHECK-ASM-AND-OBJ: pack s0, s1, s2
35+
# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09]
36+
pack s0, s1, s2
37+
# CHECK-ASM-AND-OBJ: rev8 s0, s1
38+
# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x6b]
39+
rev8 s0, s1

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,6 +1108,7 @@ R"(All available -march extensions for RISC-V
11081108
xwchc 2.2
11091109
11101110
Experimental extensions
1111+
p 0.14
11111112
zicfilp 1.0 This is a long dummy description
11121113
zicfiss 1.0
11131114
zalasr 0.1

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