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[RISCV][GISel] Correct registers classes in vector sext/zext.mir tests. NFC
The liveins were always for an LMUL=1 register class even if the first instruction used a larger regsister class. One test in zext.mir used the wrong class for the first instruction.
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2 files changed

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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -393,10 +393,10 @@ regBankSelected: true
393393
tracksRegLiveness: true
394394
body: |
395395
bb.0.entry:
396-
liveins: $v8
396+
liveins: $v8m2
397397
398398
; RV32I-LABEL: name: sext_nxv16i16_nxv16i8
399-
; RV32I: liveins: $v8
399+
; RV32I: liveins: $v8m2
400400
; RV32I-NEXT: {{ $}}
401401
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
402402
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -405,7 +405,7 @@ body: |
405405
; RV32I-NEXT: PseudoRET implicit $v8m4
406406
;
407407
; RV64I-LABEL: name: sext_nxv16i16_nxv16i8
408-
; RV64I: liveins: $v8
408+
; RV64I: liveins: $v8m2
409409
; RV64I-NEXT: {{ $}}
410410
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
411411
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -425,10 +425,10 @@ regBankSelected: true
425425
tracksRegLiveness: true
426426
body: |
427427
bb.0.entry:
428-
liveins: $v8
428+
liveins: $v8m2
429429
430430
; RV32I-LABEL: name: sext_nxv16i32_nxv16i8
431-
; RV32I: liveins: $v8
431+
; RV32I: liveins: $v8m2
432432
; RV32I-NEXT: {{ $}}
433433
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
434434
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -437,7 +437,7 @@ body: |
437437
; RV32I-NEXT: PseudoRET implicit $v8m8
438438
;
439439
; RV64I-LABEL: name: sext_nxv16i32_nxv16i8
440-
; RV64I: liveins: $v8
440+
; RV64I: liveins: $v8m2
441441
; RV64I-NEXT: {{ $}}
442442
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
443443
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -457,10 +457,10 @@ regBankSelected: true
457457
tracksRegLiveness: true
458458
body: |
459459
bb.0.entry:
460-
liveins: $v8
460+
liveins: $v8m4
461461
462462
; RV32I-LABEL: name: sext_nxv32i16_nxv32i8
463-
; RV32I: liveins: $v8
463+
; RV32I: liveins: $v8m4
464464
; RV32I-NEXT: {{ $}}
465465
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
466466
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -469,7 +469,7 @@ body: |
469469
; RV32I-NEXT: PseudoRET implicit $v8m8
470470
;
471471
; RV64I-LABEL: name: sext_nxv32i16_nxv32i8
472-
; RV64I: liveins: $v8
472+
; RV64I: liveins: $v8m4
473473
; RV64I-NEXT: {{ $}}
474474
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
475475
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -681,10 +681,10 @@ regBankSelected: true
681681
tracksRegLiveness: true
682682
body: |
683683
bb.0.entry:
684-
liveins: $v8
684+
liveins: $v8m2
685685
686686
; RV32I-LABEL: name: sext_nxv8i32_nxv8i16
687-
; RV32I: liveins: $v8
687+
; RV32I: liveins: $v8m2
688688
; RV32I-NEXT: {{ $}}
689689
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
690690
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -693,7 +693,7 @@ body: |
693693
; RV32I-NEXT: PseudoRET implicit $v8m4
694694
;
695695
; RV64I-LABEL: name: sext_nxv8i32_nxv8i16
696-
; RV64I: liveins: $v8
696+
; RV64I: liveins: $v8m2
697697
; RV64I-NEXT: {{ $}}
698698
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
699699
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -713,10 +713,10 @@ regBankSelected: true
713713
tracksRegLiveness: true
714714
body: |
715715
bb.0.entry:
716-
liveins: $v8
716+
liveins: $v8m2
717717
718718
; RV32I-LABEL: name: sext_nxv8i64_nxv8i16
719-
; RV32I: liveins: $v8
719+
; RV32I: liveins: $v8m2
720720
; RV32I-NEXT: {{ $}}
721721
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
722722
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -725,7 +725,7 @@ body: |
725725
; RV32I-NEXT: PseudoRET implicit $v8m8
726726
;
727727
; RV64I-LABEL: name: sext_nxv8i64_nxv8i16
728-
; RV64I: liveins: $v8
728+
; RV64I: liveins: $v8m2
729729
; RV64I-NEXT: {{ $}}
730730
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
731731
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -745,10 +745,10 @@ regBankSelected: true
745745
tracksRegLiveness: true
746746
body: |
747747
bb.0.entry:
748-
liveins: $v8
748+
liveins: $v8m4
749749
750750
; RV32I-LABEL: name: sext_nxv16i32_nxv16i16
751-
; RV32I: liveins: $v8
751+
; RV32I: liveins: $v8m4
752752
; RV32I-NEXT: {{ $}}
753753
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
754754
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -757,7 +757,7 @@ body: |
757757
; RV32I-NEXT: PseudoRET implicit $v8m8
758758
;
759759
; RV64I-LABEL: name: sext_nxv16i32_nxv16i16
760-
; RV64I: liveins: $v8
760+
; RV64I: liveins: $v8m4
761761
; RV64I-NEXT: {{ $}}
762762
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
763763
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -841,10 +841,10 @@ regBankSelected: true
841841
tracksRegLiveness: true
842842
body: |
843843
bb.0.entry:
844-
liveins: $v8
844+
liveins: $v8m2
845845
846846
; RV32I-LABEL: name: sext_nxv4i64_nxv4i32
847-
; RV32I: liveins: $v8
847+
; RV32I: liveins: $v8m2
848848
; RV32I-NEXT: {{ $}}
849849
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
850850
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -853,7 +853,7 @@ body: |
853853
; RV32I-NEXT: PseudoRET implicit $v8m4
854854
;
855855
; RV64I-LABEL: name: sext_nxv4i64_nxv4i32
856-
; RV64I: liveins: $v8
856+
; RV64I: liveins: $v8m2
857857
; RV64I-NEXT: {{ $}}
858858
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
859859
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -873,10 +873,10 @@ regBankSelected: true
873873
tracksRegLiveness: true
874874
body: |
875875
bb.0.entry:
876-
liveins: $v8
876+
liveins: $v8m4
877877
878878
; RV32I-LABEL: name: sext_nxv8i64_nxv8i32
879-
; RV32I: liveins: $v8
879+
; RV32I: liveins: $v8m4
880880
; RV32I-NEXT: {{ $}}
881881
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
882882
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -885,7 +885,7 @@ body: |
885885
; RV32I-NEXT: PseudoRET implicit $v8m8
886886
;
887887
; RV64I-LABEL: name: sext_nxv8i64_nxv8i32
888-
; RV64I: liveins: $v8
888+
; RV64I: liveins: $v8m4
889889
; RV64I-NEXT: {{ $}}
890890
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
891891
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -393,10 +393,10 @@ regBankSelected: true
393393
tracksRegLiveness: true
394394
body: |
395395
bb.0.entry:
396-
liveins: $v8
396+
liveins: $v8m2
397397
398398
; RV32I-LABEL: name: zext_nxv16i16_nxv16i8
399-
; RV32I: liveins: $v8
399+
; RV32I: liveins: $v8m2
400400
; RV32I-NEXT: {{ $}}
401401
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
402402
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -405,7 +405,7 @@ body: |
405405
; RV32I-NEXT: PseudoRET implicit $v8m4
406406
;
407407
; RV64I-LABEL: name: zext_nxv16i16_nxv16i8
408-
; RV64I: liveins: $v8
408+
; RV64I: liveins: $v8m2
409409
; RV64I-NEXT: {{ $}}
410410
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
411411
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -425,10 +425,10 @@ regBankSelected: true
425425
tracksRegLiveness: true
426426
body: |
427427
bb.0.entry:
428-
liveins: $v8
428+
liveins: $v8m2
429429
430430
; RV32I-LABEL: name: zext_nxv16i32_nxv16i8
431-
; RV32I: liveins: $v8
431+
; RV32I: liveins: $v8m2
432432
; RV32I-NEXT: {{ $}}
433433
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
434434
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -437,7 +437,7 @@ body: |
437437
; RV32I-NEXT: PseudoRET implicit $v8m8
438438
;
439439
; RV64I-LABEL: name: zext_nxv16i32_nxv16i8
440-
; RV64I: liveins: $v8
440+
; RV64I: liveins: $v8m2
441441
; RV64I-NEXT: {{ $}}
442442
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
443443
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -457,10 +457,10 @@ regBankSelected: true
457457
tracksRegLiveness: true
458458
body: |
459459
bb.0.entry:
460-
liveins: $v8
460+
liveins: $v8m4
461461
462462
; RV32I-LABEL: name: zext_nxv32i16_nxv32i8
463-
; RV32I: liveins: $v8
463+
; RV32I: liveins: $v8m4
464464
; RV32I-NEXT: {{ $}}
465465
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
466466
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -469,7 +469,7 @@ body: |
469469
; RV32I-NEXT: PseudoRET implicit $v8m8
470470
;
471471
; RV64I-LABEL: name: zext_nxv32i16_nxv32i8
472-
; RV64I: liveins: $v8
472+
; RV64I: liveins: $v8m4
473473
; RV64I-NEXT: {{ $}}
474474
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
475475
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -681,10 +681,10 @@ regBankSelected: true
681681
tracksRegLiveness: true
682682
body: |
683683
bb.0.entry:
684-
liveins: $v8
684+
liveins: $v8m2
685685
686686
; RV32I-LABEL: name: zext_nxv8i32_nxv8i16
687-
; RV32I: liveins: $v8
687+
; RV32I: liveins: $v8m2
688688
; RV32I-NEXT: {{ $}}
689689
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
690690
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -693,7 +693,7 @@ body: |
693693
; RV32I-NEXT: PseudoRET implicit $v8m4
694694
;
695695
; RV64I-LABEL: name: zext_nxv8i32_nxv8i16
696-
; RV64I: liveins: $v8
696+
; RV64I: liveins: $v8m2
697697
; RV64I-NEXT: {{ $}}
698698
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
699699
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -713,26 +713,26 @@ regBankSelected: true
713713
tracksRegLiveness: true
714714
body: |
715715
bb.0.entry:
716-
liveins: $v8
716+
liveins: $v8m2
717717
718718
; RV32I-LABEL: name: zext_nxv8i64_nxv8i16
719-
; RV32I: liveins: $v8
719+
; RV32I: liveins: $v8m2
720720
; RV32I-NEXT: {{ $}}
721-
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4
721+
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
722722
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
723723
; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */
724724
; RV32I-NEXT: $v8m8 = COPY %1
725725
; RV32I-NEXT: PseudoRET implicit $v8m8
726726
;
727727
; RV64I-LABEL: name: zext_nxv8i64_nxv8i16
728-
; RV64I: liveins: $v8
728+
; RV64I: liveins: $v8m2
729729
; RV64I-NEXT: {{ $}}
730-
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m4
730+
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
731731
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
732732
; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */
733733
; RV64I-NEXT: $v8m8 = COPY %1
734734
; RV64I-NEXT: PseudoRET implicit $v8m8
735-
%0:vrb(<vscale x 8 x s16>) = COPY $v8m4
735+
%0:vrb(<vscale x 8 x s16>) = COPY $v8m2
736736
%1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s16>)
737737
$v8m8 = COPY %1(<vscale x 8 x s64>)
738738
PseudoRET implicit $v8m8
@@ -745,10 +745,10 @@ regBankSelected: true
745745
tracksRegLiveness: true
746746
body: |
747747
bb.0.entry:
748-
liveins: $v8
748+
liveins: $v8m4
749749
750750
; RV32I-LABEL: name: zext_nxv16i32_nxv16i16
751-
; RV32I: liveins: $v8
751+
; RV32I: liveins: $v8m4
752752
; RV32I-NEXT: {{ $}}
753753
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
754754
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -757,7 +757,7 @@ body: |
757757
; RV32I-NEXT: PseudoRET implicit $v8m8
758758
;
759759
; RV64I-LABEL: name: zext_nxv16i32_nxv16i16
760-
; RV64I: liveins: $v8
760+
; RV64I: liveins: $v8m4
761761
; RV64I-NEXT: {{ $}}
762762
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
763763
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -841,10 +841,10 @@ regBankSelected: true
841841
tracksRegLiveness: true
842842
body: |
843843
bb.0.entry:
844-
liveins: $v8
844+
liveins: $v8m2
845845
846846
; RV32I-LABEL: name: zext_nxv4i64_nxv4i32
847-
; RV32I: liveins: $v8
847+
; RV32I: liveins: $v8m2
848848
; RV32I-NEXT: {{ $}}
849849
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
850850
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -853,7 +853,7 @@ body: |
853853
; RV32I-NEXT: PseudoRET implicit $v8m4
854854
;
855855
; RV64I-LABEL: name: zext_nxv4i64_nxv4i32
856-
; RV64I: liveins: $v8
856+
; RV64I: liveins: $v8m2
857857
; RV64I-NEXT: {{ $}}
858858
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2
859859
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
@@ -873,10 +873,10 @@ regBankSelected: true
873873
tracksRegLiveness: true
874874
body: |
875875
bb.0.entry:
876-
liveins: $v8
876+
liveins: $v8m4
877877
878878
; RV32I-LABEL: name: zext_nxv8i64_nxv8i32
879-
; RV32I: liveins: $v8
879+
; RV32I: liveins: $v8m4
880880
; RV32I-NEXT: {{ $}}
881881
; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
882882
; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
@@ -885,7 +885,7 @@ body: |
885885
; RV32I-NEXT: PseudoRET implicit $v8m8
886886
;
887887
; RV64I-LABEL: name: zext_nxv8i64_nxv8i32
888-
; RV64I: liveins: $v8
888+
; RV64I: liveins: $v8m4
889889
; RV64I-NEXT: {{ $}}
890890
; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4
891891
; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF

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