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[LLVM][AArch64]CFINV - Add UNPREDICTABLE behaviour if CRm is not zero
Now CFINV follows AXFLAGS behaviour for CRm. It looks like (0) in the instruction encoding means that the behaviour is UNPREDICTABLE if that bit is not zero.
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‎0001-Add-FP8-ACLE-macros-implementation.patch

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From f31b5b2fa13f047ebef3f5a3dab35382379b8914 Mon Sep 17 00:00:00 2001
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From: CarolineConcatto <[email protected]>
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Date: Mon, 19 May 2025 18:21:28 +0000
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Subject: [PATCH] Add FP8 ACLE macros implementation
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This patch implements the macros described in the ACLE[1]
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[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#modal-8-bit-floating-point-extensions
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---
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clang/lib/Basic/Targets/AArch64.cpp | 59 +++++++++++++++++++
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clang/lib/Basic/Targets/AArch64.h | 9 +++
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.../Preprocessor/aarch64-target-features.c | 31 ++++++++++
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3 files changed, 99 insertions(+)
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diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
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index e1f6c7b834dc..7267b17704a4 100644
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--- a/clang/lib/Basic/Targets/AArch64.cpp
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+++ b/clang/lib/Basic/Targets/AArch64.cpp
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@@ -596,6 +596,33 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
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if (HasSMEB16B16)
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Builder.defineMacro("__ARM_FEATURE_SME_B16B16", "1");
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+ if (HasFP8)
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+ Builder.defineMacro("__ARM_FEATURE_FP8", "1");
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+
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+ if (HasFP8FMA)
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+ Builder.defineMacro("__ARM_FEATURE_FP8FMA", "1");
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+
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+ if (HasFP8DOT2)
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+ Builder.defineMacro("__ARM_FEATURE_FP8DOT2", "1");
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+
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+ if (HasFP8DOT4)
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+ Builder.defineMacro("__ARM_FEATURE_FP8DOT4", "1");
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+
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+ if (HasSSVE_FP8DOT2)
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+ Builder.defineMacro("__ARM_FEATURE_SSVE_FP8DOT2", "1");
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+
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+ if (HasSSVE_FP8DOT4)
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+ Builder.defineMacro("__ARM_FEATURE_SSVE_FP8DOT4", "1");
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+
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+ if (HasSSVE_FP8FMA)
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+ Builder.defineMacro("__ARM_FEATURE_SSVE_FP8FMA", "1");
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+
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+ if (HasSME_F8F32)
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+ Builder.defineMacro("__ARM_FEATURE_SME_F8F32", "1");
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+
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+ if (HasSME_F8F16)
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+ Builder.defineMacro("__ARM_FEATURE_SME_F8F16", "1");
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+
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if (HasCRC)
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Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
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@@ -885,6 +912,15 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
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.Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
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.Case("wfxt", HasWFxT)
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.Case("rcpc3", HasRCPC3)
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+ .Case("fp8", HasFP8)
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+ .Case("fp8fma", HasFP8FMA)
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+ .Case("fp8dot2", HasFP8DOT2)
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+ .Case("fp8dot4", HasFP8DOT4)
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+ .Case("ssve-fp8dot2", HasSSVE_FP8DOT2)
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+ .Case("ssve-fp8dot4", HasSSVE_FP8DOT4)
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+ .Case("ssve-fp8fma", HasSSVE_FP8FMA)
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+ .Case("sme-f8f32", HasSME_F8F32)
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+ .Case("sme-f8f16", HasSME_F8F16)
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.Default(false);
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}
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@@ -1046,6 +1082,29 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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HasSVEB16B16 = true;
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HasSMEB16B16 = true;
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}
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+
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+ if (Feature == "+fp8")
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+ HasFP8 = true;
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+ if (Feature == "+fp8fma")
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+ HasFP8FMA = true;
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+ if (Feature == "+fp8dot2")
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+ HasFP8DOT2 = true;
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+ if (Feature == "+fp8dot4")
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+ HasFP8DOT4 = true;
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+ if (Feature == "+ssve-fp8dot2")
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+ HasSSVE_FP8DOT2 = true;
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+ if (Feature == "+ssve-fp8dot4")
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+ HasSSVE_FP8DOT4 = true;
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+ if (Feature == "+ssve-fp8fma")
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+ HasSSVE_FP8FMA = true;
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+ if (Feature == "+sme-f8f32") {
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+ HasSME2 = true;
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+ HasSME_F8F32 = true;
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+ }
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+ if (Feature == "+sme-f8f16") {
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+ HasSME2 = true;
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+ HasSME_F8F16 = true;
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+ }
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if (Feature == "+sb")
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HasSB = true;
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if (Feature == "+predres")
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diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
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index 6eeac69af20d..7230f22d5bb8 100644
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--- a/clang/lib/Basic/Targets/AArch64.h
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+++ b/clang/lib/Basic/Targets/AArch64.h
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@@ -106,6 +106,15 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
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bool HasSMEF16F16 = false;
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bool HasSMEB16B16 = false;
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bool HasSME2p1 = false;
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+ bool HasFP8 = false;
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+ bool HasFP8FMA = false;
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+ bool HasFP8DOT2 = false;
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+ bool HasFP8DOT4 = false;
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+ bool HasSSVE_FP8DOT2 = false;
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+ bool HasSSVE_FP8DOT4 = false;
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+ bool HasSSVE_FP8FMA = false;
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+ bool HasSME_F8F32 = false;
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+ bool HasSME_F8F16 = false;
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bool HasSB = false;
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bool HasPredRes = false;
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bool HasSSBS = false;
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diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c
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index 3f801c434494..52045d216262 100644
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--- a/clang/test/Preprocessor/aarch64-target-features.c
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+++ b/clang/test/Preprocessor/aarch64-target-features.c
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@@ -744,3 +744,34 @@
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// CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
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// CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
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// CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
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+//
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+// RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8 %s
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+// CHECK-FP8: __ARM_FEATURE_FP8 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+fp8fma -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8FMA %s
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+// CHECK-FP8FMA: __ARM_FEATURE_FP8FMA 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+fp8dot2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8DOT2 %s
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+// CHECK-FP8DOT2: __ARM_FEATURE_FP8DOT2 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+fp8dot4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8DOT4 %s
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+// CHECK-FP8DOT4: __ARM_FEATURE_FP8DOT4 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+ssve-fp8dot2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SSVE-FP8DOT2 %s
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+// CHECK-SSVE-FP8DOT2: __ARM_FEATURE_SSVE_FP8DOT2 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+ssve-fp8dot4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SSVE-FP8DOT4 %s
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+// CHECK-SSVE-FP8DOT4: __ARM_FEATURE_SSVE_FP8DOT4 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+ssve-fp8fma -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SSVE-FP8FMA %s
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+// CHECK-SSVE-FP8FMA: __ARM_FEATURE_SSVE_FP8FMA 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+sme-f8f32 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SMEF8F32 %s
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+// CHECK-SMEF8F32: __ARM_FEATURE_LOCALLY_STREAMING 1
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+// CHECK-SMEF8F32: __ARM_FEATURE_SME2 1
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+// CHECK-SMEF8F32: __ARM_FEATURE_SME_F8F32 1
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+
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+// RUN: %clang --target=aarch64 -march=armv9-a+sme-f8f16 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SMEF8F16 %s
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+// CHECK-SMEF8F16: __ARM_FEATURE_LOCALLY_STREAMING 1
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+// CHECK-SMEF8F16: __ARM_FEATURE_SME2 1
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+// CHECK-SMEF8F16: __ARM_FEATURE_SME_F8F16 1
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--
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2.43.0
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

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@@ -2096,6 +2096,7 @@ def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
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let Predicates = [HasFlagM], Defs = [NZCV], Uses = [NZCV] in {
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def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
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let Inst{20-5} = 0b0000001000000000;
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let Unpredictable{11-8} = 0b1111;
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}
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def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;
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def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;

‎llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt

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# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
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[0x1f,0x40,0x00,0xd5]
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[0x1f,0x4f,0x00,0xd5]
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[0x2d,0x08,0x00,0x3a]
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[0x2d,0x48,0x00,0x3a]
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[0x2f,0x84,0x1f,0xba]
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#CHECK: cfinv
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#CHECK: cfinv
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#CHECK: setf8 w1
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#CHECK: setf16 w1

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