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[RISCV] Rename suffixes on VCPOP/VMSBF/VMSET/etc pseudos. NFC (#119785)
These are suffixed with B1, B2, B4, B8, B16, B32, or B64 which I think these were supposed to match the naming of the vbool types from C where the number should be SEW/LMUL. So the smallest mask is 64 and the largest is 1. This provides a compact syntax for describing the 7 possible ratios between LMUL and SEW. We had the instruction names in the opposite order.
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7 files changed

+64
-64
lines changed

7 files changed

+64
-64
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1673,13 +1673,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
16731673
VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix; \
16741674
VMSetOpcode = RISCV::PseudoVMSET_M_##suffix_b; \
16751675
break;
1676-
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F8, MF8, B1)
1677-
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F4, MF4, B2)
1678-
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F2, MF2, B4)
1676+
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F8, MF8, B64)
1677+
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F4, MF4, B32)
1678+
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_F2, MF2, B16)
16791679
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_1, M1, B8)
1680-
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_2, M2, B16)
1681-
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_4, M4, B32)
1682-
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_8, M8, B64)
1680+
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_2, M2, B4)
1681+
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_4, M4, B2)
1682+
CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_8, M8, B1)
16831683
#undef CASE_VMSLT_VMNAND_VMSET_OPCODES
16841684
}
16851685
SDValue SEW = CurDAG->getTargetConstant(
@@ -1751,13 +1751,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
17511751
VMSGTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix##_MASK \
17521752
: RISCV::PseudoVMSGT_VX_##suffix##_MASK; \
17531753
break;
1754-
CASE_VMSLT_OPCODES(LMUL_F8, MF8, B1)
1755-
CASE_VMSLT_OPCODES(LMUL_F4, MF4, B2)
1756-
CASE_VMSLT_OPCODES(LMUL_F2, MF2, B4)
1754+
CASE_VMSLT_OPCODES(LMUL_F8, MF8, B64)
1755+
CASE_VMSLT_OPCODES(LMUL_F4, MF4, B32)
1756+
CASE_VMSLT_OPCODES(LMUL_F2, MF2, B16)
17571757
CASE_VMSLT_OPCODES(LMUL_1, M1, B8)
1758-
CASE_VMSLT_OPCODES(LMUL_2, M2, B16)
1759-
CASE_VMSLT_OPCODES(LMUL_4, M4, B32)
1760-
CASE_VMSLT_OPCODES(LMUL_8, M8, B64)
1758+
CASE_VMSLT_OPCODES(LMUL_2, M2, B4)
1759+
CASE_VMSLT_OPCODES(LMUL_4, M4, B2)
1760+
CASE_VMSLT_OPCODES(LMUL_8, M8, B1)
17611761
#undef CASE_VMSLT_OPCODES
17621762
}
17631763
// Mask operations use the LMUL from the mask type.

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -422,13 +422,13 @@ class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {
422422

423423
defset list<MTypeInfo> AllMasks = {
424424
// vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
425-
def : MTypeInfo<vbool64_t, V_MF8, "B1">;
426-
def : MTypeInfo<vbool32_t, V_MF4, "B2">;
427-
def : MTypeInfo<vbool16_t, V_MF2, "B4">;
425+
def : MTypeInfo<vbool64_t, V_MF8, "B64">;
426+
def : MTypeInfo<vbool32_t, V_MF4, "B32">;
427+
def : MTypeInfo<vbool16_t, V_MF2, "B16">;
428428
def : MTypeInfo<vbool8_t, V_M1, "B8">;
429-
def : MTypeInfo<vbool4_t, V_M2, "B16">;
430-
def : MTypeInfo<vbool2_t, V_M4, "B32">;
431-
def : MTypeInfo<vbool1_t, V_M8, "B64">;
429+
def : MTypeInfo<vbool4_t, V_M2, "B4">;
430+
def : MTypeInfo<vbool2_t, V_M4, "B2">;
431+
def : MTypeInfo<vbool1_t, V_M8, "B1">;
432432
}
433433

434434
class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti> {

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ body: |
1111
bb.1:
1212
; CHECK-LABEL: name: negative_vl
1313
; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
14-
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
15-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
14+
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */
15+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
1616
; CHECK-NEXT: PseudoRET implicit $v0
1717
%0:gprb(s32) = G_CONSTANT i32 -2
1818
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
@@ -31,8 +31,8 @@ body: |
3131
; CHECK: liveins: $x10
3232
; CHECK-NEXT: {{ $}}
3333
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
34-
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
35-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
34+
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */
35+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
3636
; CHECK-NEXT: PseudoRET implicit $v0
3737
%0:gprb(s32) = COPY $x10
3838
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
@@ -48,8 +48,8 @@ tracksRegLiveness: true
4848
body: |
4949
bb.1:
5050
; CHECK-LABEL: name: nonzero_vl
51-
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
52-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
51+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */
52+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
5353
; CHECK-NEXT: PseudoRET implicit $v0
5454
%0:gprb(s32) = G_CONSTANT i32 1
5555
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
@@ -65,8 +65,8 @@ tracksRegLiveness: true
6565
body: |
6666
bb.1:
6767
; CHECK-LABEL: name: zero_vl
68-
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
69-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
68+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */
69+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
7070
; CHECK-NEXT: PseudoRET implicit $v0
7171
%0:gprb(s32) = G_CONSTANT i32 0
7272
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ body: |
1111
bb.1:
1212
; CHECK-LABEL: name: negative_vl
1313
; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
14-
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
15-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
14+
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */
15+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
1616
; CHECK-NEXT: PseudoRET implicit $v0
1717
%0:gprb(s64) = G_CONSTANT i64 -2
1818
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
@@ -31,8 +31,8 @@ body: |
3131
; CHECK: liveins: $x10
3232
; CHECK-NEXT: {{ $}}
3333
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
34-
; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
35-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
34+
; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */
35+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
3636
; CHECK-NEXT: PseudoRET implicit $v0
3737
%0:gprb(s64) = COPY $x10
3838
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
@@ -48,8 +48,8 @@ tracksRegLiveness: true
4848
body: |
4949
bb.1:
5050
; CHECK-LABEL: name: nonzero_vl
51-
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
52-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
51+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */
52+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
5353
; CHECK-NEXT: PseudoRET implicit $v0
5454
%0:gprb(s64) = G_CONSTANT i64 1
5555
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
@@ -65,8 +65,8 @@ tracksRegLiveness: true
6565
body: |
6666
bb.1:
6767
; CHECK-LABEL: name: zero_vl
68-
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
69-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
68+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */
69+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
7070
; CHECK-NEXT: PseudoRET implicit $v0
7171
%0:gprb(s64) = G_CONSTANT i64 0
7272
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ tracksRegLiveness: true
1010
body: |
1111
bb.1:
1212
; CHECK-LABEL: name: splat_zero_nxv1i1
13-
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
14-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
13+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
14+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
1515
; CHECK-NEXT: PseudoRET implicit $v0
1616
%0:gprb(s32) = G_CONSTANT i32 -1
1717
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
@@ -27,8 +27,8 @@ tracksRegLiveness: true
2727
body: |
2828
bb.1:
2929
; CHECK-LABEL: name: splat_zero_nxv2i1
30-
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
31-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
30+
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
31+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
3232
; CHECK-NEXT: PseudoRET implicit $v0
3333
%0:gprb(s32) = G_CONSTANT i32 -1
3434
%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
@@ -44,8 +44,8 @@ tracksRegLiveness: true
4444
body: |
4545
bb.1:
4646
; CHECK-LABEL: name: splat_zero_nxv4i1
47-
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
48-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
47+
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
48+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
4949
; CHECK-NEXT: PseudoRET implicit $v0
5050
%0:gprb(s32) = G_CONSTANT i32 -1
5151
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
@@ -78,8 +78,8 @@ tracksRegLiveness: true
7878
body: |
7979
bb.1:
8080
; CHECK-LABEL: name: splat_zero_nxv16i1
81-
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
82-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
81+
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
82+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
8383
; CHECK-NEXT: PseudoRET implicit $v0
8484
%0:gprb(s32) = G_CONSTANT i32 -1
8585
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
@@ -95,8 +95,8 @@ tracksRegLiveness: true
9595
body: |
9696
bb.1:
9797
; CHECK-LABEL: name: splat_zero_nxv32i1
98-
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
99-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
98+
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
99+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
100100
; CHECK-NEXT: PseudoRET implicit $v0
101101
%0:gprb(s32) = G_CONSTANT i32 -1
102102
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
@@ -112,8 +112,8 @@ tracksRegLiveness: true
112112
body: |
113113
bb.1:
114114
; CHECK-LABEL: name: splat_zero_nxv64i1
115-
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
116-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
115+
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
116+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
117117
; CHECK-NEXT: PseudoRET implicit $v0
118118
%0:gprb(s32) = G_CONSTANT i32 -1
119119
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ tracksRegLiveness: true
1010
body: |
1111
bb.1:
1212
; CHECK-LABEL: name: splat_zero_nxv1i1
13-
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
14-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
13+
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
14+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
1515
; CHECK-NEXT: PseudoRET implicit $v0
1616
%0:gprb(s64) = G_CONSTANT i64 -1
1717
%1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
@@ -27,8 +27,8 @@ tracksRegLiveness: true
2727
body: |
2828
bb.1:
2929
; CHECK-LABEL: name: splat_zero_nxv2i1
30-
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
31-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
30+
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
31+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
3232
; CHECK-NEXT: PseudoRET implicit $v0
3333
%0:gprb(s64) = G_CONSTANT i64 -1
3434
%1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
@@ -44,8 +44,8 @@ tracksRegLiveness: true
4444
body: |
4545
bb.1:
4646
; CHECK-LABEL: name: splat_zero_nxv4i1
47-
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
48-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
47+
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
48+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
4949
; CHECK-NEXT: PseudoRET implicit $v0
5050
%0:gprb(s64) = G_CONSTANT i64 -1
5151
%1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
@@ -78,8 +78,8 @@ tracksRegLiveness: true
7878
body: |
7979
bb.1:
8080
; CHECK-LABEL: name: splat_zero_nxv16i1
81-
; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
82-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
81+
; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
82+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
8383
; CHECK-NEXT: PseudoRET implicit $v0
8484
%0:gprb(s64) = G_CONSTANT i64 -1
8585
%1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
@@ -95,8 +95,8 @@ tracksRegLiveness: true
9595
body: |
9696
bb.1:
9797
; CHECK-LABEL: name: splat_zero_nxv32i1
98-
; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
99-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
98+
; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
99+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
100100
; CHECK-NEXT: PseudoRET implicit $v0
101101
%0:gprb(s64) = G_CONSTANT i64 -1
102102
%1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
@@ -112,8 +112,8 @@ tracksRegLiveness: true
112112
body: |
113113
bb.1:
114114
; CHECK-LABEL: name: splat_zero_nxv64i1
115-
; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
116-
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
115+
; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
116+
; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
117117
; CHECK-NEXT: PseudoRET implicit $v0
118118
%0:gprb(s64) = G_CONSTANT i64 -1
119119
%1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -512,9 +512,9 @@ body: |
512512
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
513513
; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
514514
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
515-
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSEQ_VI_MF2_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
515+
; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
516516
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
517-
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B1_]], $x0, %bb.3
517+
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3
518518
; CHECK-NEXT: PseudoBR %bb.2
519519
; CHECK-NEXT: {{ $}}
520520
; CHECK-NEXT: bb.2:
@@ -543,7 +543,7 @@ body: |
543543
%5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5
544544
$v0 = COPY %5
545545
%6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0
546-
%7:gpr = PseudoVCPOP_M_B1 %5, -1, 0
546+
%7:gpr = PseudoVCPOP_M_B64 %5, -1, 0
547547
%8:gpr = COPY $x0
548548
BEQ killed %7, %8, %bb.3
549549
PseudoBR %bb.2
@@ -906,8 +906,8 @@ body: |
906906
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
907907
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
908908
; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
909-
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
910-
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B1_]], $x0, %bb.3
909+
; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
910+
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3
911911
; CHECK-NEXT: PseudoBR %bb.2
912912
; CHECK-NEXT: {{ $}}
913913
; CHECK-NEXT: bb.2:
@@ -952,7 +952,7 @@ body: |
952952
%61:gpr = ADD %12, %26
953953
%27:vr = PseudoVADD_VX_M1 undef $noreg, %10, killed %61, -1, 6, 0
954954
%62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6
955-
%63:gpr = PseudoVCPOP_M_B1 %62, -1, 0
955+
%63:gpr = PseudoVCPOP_M_B64 %62, -1, 0
956956
%64:gpr = COPY $x0
957957
BEQ killed %63, %64, %bb.3
958958
PseudoBR %bb.2

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